Merge branch 'master' of git://git.denx.de/u-boot-arm

Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR

Conflicts:
	arch/arm/include/asm/arch-omap5/omap.h

Signed-off-by: Tom Rini <trini@ti.com>

1 files changed, 55 insertions, 4 deletions

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index baeef4e5b..0dbe81b59 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -29,7 +29,7 @@
 
 #include <common.h>
 
-#define NUM_SYS_CLKS	8
+#define NUM_SYS_CLKS	7
 
 struct prcm_regs {
 	/* cm1.ckgen */
@@ -242,6 +242,8 @@ struct prcm_regs {
 	u32 cm_l3init_fsusb_clkctrl;
 	u32 cm_l3init_ocp2scp1_clkctrl;
 
+	u32 prm_irqstatus_mpu_2;
+
 	/* cm2.l4per */
 	u32 cm_l4per_clkstctrl;
 	u32 cm_l4per_dynamicdep;
@@ -301,6 +303,7 @@ struct prcm_regs {
 	/* l4 wkup regs */
 	u32 cm_abe_pll_ref_clksel;
 	u32 cm_sys_clksel;
+	u32 cm_abe_pll_sys_clksel;
 	u32 cm_wkup_clkstctrl;
 	u32 cm_wkup_l4wkup_clkctrl;
 	u32 cm_wkup_wdtimer1_clkctrl;
@@ -328,6 +331,8 @@ struct prcm_regs {
 	u32 prm_sldo_mpu_ctrl;
 	u32 prm_sldo_mm_setup;
 	u32 prm_sldo_mm_ctrl;
+	u32 prm_abbldo_mpu_setup;
+	u32 prm_abbldo_mpu_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -346,10 +351,15 @@ struct prcm_regs {
 	u32 cm_l3init_usbphy_clkctrl;
 	u32 cm_l4per_mcbsp4_clkctrl;
 	u32 prm_vc_cfg_channel;
+
+	/* SCRM stuff, used by some boards */
+	u32 scrm_auxclk0;
+	u32 scrm_auxclk1;
 };
 
 struct omap_sys_ctrl_regs {
 	u32 control_status;
+	u32 control_std_fuse_opp_vdd_mpu_2;
 	u32 control_core_mmr_lock1;
 	u32 control_core_mmr_lock2;
 	u32 control_core_mmr_lock3;
@@ -362,6 +372,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ldosram_iva_voltage_ctrl;
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
+	u32 control_usbotghs_ctrl;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
@@ -394,6 +405,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_ddrio_0;
 	u32 control_ddrio_1;
 	u32 control_ddrio_2;
+	u32 control_ddr_control_ext_0;
 	u32 control_lpddr2io1_0;
 	u32 control_lpddr2io1_1;
 	u32 control_lpddr2io1_2;
@@ -419,6 +431,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_port_emif2_sdram_config;
 	u32 control_emif1_sdram_config_ext;
 	u32 control_emif2_sdram_config_ext;
+	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;
@@ -494,11 +507,25 @@ struct pmic_data {
 	u32 start_code;
 	unsigned gpio;
 	int gpio_en;
+	u32 i2c_slave_addr;
+	void (*pmic_bus_init)(void);
+	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+};
+
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg:	register address for efuse
+ * @reg_bits:	Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+	u32 reg;
+	u8 reg_bits;
 };
 
 struct volts {
 	u32 value;
 	u32 addr;
+	struct volts_efuse_data efuse;
 	struct pmic_data *pmic;
 };
 
@@ -506,6 +533,9 @@ struct vcores_data {
 	struct volts mpu;
 	struct volts core;
 	struct volts mm;
+	struct volts gpu;
+	struct volts eve;
+	struct volts iva;
 };
 
 extern struct prcm_regs const **prcm;
@@ -545,9 +575,9 @@ void enable_non_essential_clocks(void);
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-
-/* Max value for DPLL multiplier M */
-#define OMAP_DPLL_MAX_N	127
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+	       u32 txdone, u32 txdone_mask, u32 opp);
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
 /* HW Init Context */
 #define OMAP_INIT_CONTEXT_SPL			0
@@ -555,11 +585,32 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
+/* ABB */
+#define OMAP_ABB_NOMINAL_OPP		0
+#define OMAP_ABB_FAST_OPP		1
+#define OMAP_ABB_SLOW_OPP		3
+#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK		(0x1 << 0)
+#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK		(0x1 << 2)
+#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK		(0x1 << 6)
+#define OMAP_ABB_SETUP_SR2EN_MASK			(0x1 << 0)
+#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK		(0x1 << 2)
+#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK		(0xff << 8)
+
 static inline u32 omap_revision(void)
 {
 	extern u32 *const omap_si_rev;
 	return *omap_si_rev;
 }
+
+#define OMAP54xx	0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
 #endif
 
 /*