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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-09-04 14:06:56 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-09-04 14:06:56 +0200 |
| commit | e62d5fb0da76ef168e90cae9bbbda80349aaf137 (patch) | |
| tree | b5c338d17f0633b7ec2e27d4d8b82dcf153a5281 /arch/arm/include/asm/arch-omap5/omap.h | |
| parent | 4eef93da262048eb1118e726b3ec5b8ebd3c6c91 (diff) | |
| parent | 901ce27c6f018992b7dd6c08d3c98cf217cc4c96 (diff) | |
| download | olio-uboot-2014.01-e62d5fb0da76ef168e90cae9bbbda80349aaf137.tar.xz olio-uboot-2014.01-e62d5fb0da76ef168e90cae9bbbda80349aaf137.zip | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/omap.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 597c692b9..e9a51d340 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -153,6 +153,15 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ #ifdef CONFIG_DRA7XX #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ @@ -160,7 +169,7 @@ struct s32ktimer { #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 |