diff options
Diffstat (limited to 'cpu/mpc8xxx/ddr/options.c')
| -rw-r--r-- | cpu/mpc8xxx/ddr/options.c | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 29d414343..db442918e 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -96,10 +96,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, */ #if defined(CONFIG_FSL_DDR1) popts->DQS_config = 0; -#elif defined(CONFIG_FSL_DDR2) +#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) popts->DQS_config = 1; -#else -#error "Fix DQS for DDR3" #endif /* Choose self-refresh during sleep. */ @@ -112,7 +110,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->data_bus_width = 0; /* Choose burst length. */ - popts->burst_length = 4; /* has to be 4 for DDR2 */ +#if defined(CONFIG_FSL_DDR3) + popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ +#else + popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ +#endif + + /* Choose ddr controller address mirror mode */ +#if defined(CONFIG_FSL_DDR3) + popts->mirrored_dimm = pdimm[0].mirrored_dimm; +#endif /* Global Timing Parameters. */ debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); @@ -181,7 +189,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->tFAW_window_four_activates_ps = 37500; #elif defined(CONFIG_FSL_DDR3) -#error "FIXME determine four activates for DDR3" + popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps; +#endif + popts->zq_en = 0; + popts->wrlvl_en = 0; +#if defined(CONFIG_FSL_DDR3) + /* + * due to ddr3 dimm is fly-by topology + * we suggest to enable write leveling to + * meet the tQDSS under different loading. + */ + popts->wrlvl_en = 1; #endif /* |