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-rw-r--r--board/olio/h1/h1.c72
-rw-r--r--board/olio/h1/h1.c.bak105
-rw-r--r--board/olio/h1/pinmux.h33
3 files changed, 200 insertions, 10 deletions
diff --git a/board/olio/h1/h1.c b/board/olio/h1/h1.c
index e69797638..43bc998fd 100644
--- a/board/olio/h1/h1.c
+++ b/board/olio/h1/h1.c
@@ -26,9 +26,43 @@
#include <command.h>
#include <power/tps65910.h>
#include <i2c.h>
+#include <asm/arch/musb.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/am35x_def.h>
+#include <i2c.h>
+#include <linux/compiler.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <asm/omap_musb.h>
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
+#define USB_CS 17
+
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -154,6 +188,38 @@ static int accel_regulator_init(void)
return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_VDIG1_REG, 1, &buf, 1);
}
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &musb_config,
+ .power = 100,
+ .platform_ops = &omap2430_ops,
+ .board_data = &musb_board_data,
+};
+
+
+static void olio_evm_musb_init(void)
+{
+ printf("musb mode %s \n", musb_plat.mode == MUSB_PERIPHERAL ? "MUSB_PERIPHERAL" : "MUSB_HOST");
+ musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
@@ -174,6 +240,12 @@ int misc_init_r(void)
dieid_num_r();
+ printf("debug usb_data0 %d mode %d \n", CONTROL_PADCONF_HSUSB0_DATA0 , (IEN | PD | M0));
+ gpio_request(USB_CS, "usb_cs");
+ gpio_direction_output(USB_CS, 1);
+
+ olio_evm_musb_init();
+
return 0;
}
diff --git a/board/olio/h1/h1.c.bak b/board/olio/h1/h1.c.bak
new file mode 100644
index 000000000..325e4ded1
--- /dev/null
+++ b/board/olio/h1/h1.c.bak
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2004-2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/errno.h>
+#include "h1.h"
+#include <command.h>
+#include <power/tps65910.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_H1;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int pop_mfr, pop_id;
+
+ /*
+ * We need to identify what PoP memory is on the board so that
+ * we know what timings to use. If we can't identify it then
+ * we know it's an xM. To map the ID values please see nand_ids.c
+ */
+ identify_nand_chip(&pop_mfr, &pop_id);
+
+ timings->mr = 0x00000032;
+ timings->mcfg = MICRON_V_MCFG_200(512 << 20); /* OLIO, mfj: not sure what this should be */
+ timings->ctrla = 0x7AE1B4C6;
+ timings->ctrlb = 0x00021217;
+ timings->rfr_ctrl = 0x00062701;
+
+ /* 128MB DDR - safe settings from Beagle
+ timings->mr = MICRON_V_MR_165;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ */
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+ struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+
+ //MUX_BEAGLE_XM();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_EVM();
+}
diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h
index 23cfede2e..3861c3bad 100644
--- a/board/olio/h1/pinmux.h
+++ b/board/olio/h1/pinmux.h
@@ -146,15 +146,15 @@ MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \
MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\
MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IEN | PU | M7 )) /* safe_mode */\
@@ -312,5 +312,18 @@ MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PU | M4 )) /* gpio_146 */\
MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, (IEN | PU | M0 )) /* uart3_cts_rctx */\
MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | PU | M0 )) /* uart3_rts_sd */\
MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PU | M0 )) /* uart3_rx_irrx */\
-MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PI | M0 )) /* hsusb0_clk */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PI | M0)) /* hsusb0_data0 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PI | M0)) /* hsusb0_data1 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PI | M0)) /* hsusb0_data2 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PI | M0)) /* hsusb0_data3 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PI | M0)) /* hsusb0_data4 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PI | M0)) /* hsusb0_data5 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PI | M0)) /* hsusb0_data6 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PI | M0)) /* hsusb0_data7 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PI | M0)) /*hsusb0_dir */ \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PI | M0)) /*hsusb0_stp */ \
+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PI | M0)) /*hsusb0_nxt */ \
+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IDIS | PI | M4)) /* gpio_17 */
#endif
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 03:07:26 +0000