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-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c21
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c52
-rw-r--r--board/freescale/mpc8540ads/tlb.c19
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c43
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c17
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c38
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c45
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c52
-rw-r--r--board/freescale/mpc8560ads/tlb.c19
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c38
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c36
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c19
-rw-r--r--board/freescale/p1022ds/p1022ds.c13
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c15
-rw-r--r--board/freescale/p2020ds/p2020ds.c34
15 files changed, 10 insertions, 451 deletions
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index bd80cb776..58dc564ee 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void);
-
int board_early_init_f (void)
{
#ifdef CONFIG_MMC
@@ -98,25 +96,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index d354a26f6..deab811bd 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
int checkboard (void)
{
@@ -61,54 +59,6 @@ int checkboard (void)
return 0;
}
-
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
/*
* Initialize Local Bus
*/
@@ -232,7 +182,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index a9925d542..adcc0ade0 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 59ec60446..59df2bdb3 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
/*
* I/O Port configuration table
@@ -242,48 +241,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 2b6900c08..caea2f4d9 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -68,23 +68,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index ebeb89749..a4a35fa3b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -42,7 +42,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
-void sdram_init(void);
int checkboard (void)
{
@@ -75,43 +74,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index edaba26f5..5fe7f1398 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
-void sdram_init(void);
/*
* I/O Port configuration table
@@ -240,50 +239,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 2ae0459fe..49701efda 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
/*
@@ -266,54 +264,6 @@ int checkboard (void)
return 0;
}
-
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint temp_ddrdll = 0;
-
- /*
- * Work around to stabilize DDR DLL
- */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
- }
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
- /*
- * Initialize SDRAM.
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
-
/*
* Initialize Local Bus
*/
@@ -437,7 +387,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index a9925d542..adcc0ade0 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- /*
- * TLB 8, 9: 128M DDR
- * 0x00000000 64M DDR System memory
- * 0x04000000 64M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
-#error("Update the number of table entries in tlb1_entry")
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_64M, 1),
-#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 71cfbf0f3..85885fc4f 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -101,7 +101,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
};
void local_bus_init(void);
-void sdram_init(void);
int board_early_init_f (void)
{
@@ -138,43 +137,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- {
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
-
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay(200);
- }
-#endif
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- /*
- * SDRAM Initialization
- */
- sdram_init();
-
- puts(" DDR: ");
- return dram_size;
-}
-
/*
* Initialize Local Bus
*/
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 9700b8c6e..07db16aa0 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -45,8 +45,6 @@
#include "../common/pq-mds-pib.h"
#endif
-phys_size_t fixed_sdram(void);
-
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDC */
{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
@@ -245,40 +243,6 @@ int checkboard (void)
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
- /*
- * Work around to stabilize DDR DLL MSYNC_IN.
- * Errata DDR9 seems to have been fixed.
- * This is now the workaround for Errata DDR11:
- * Override DLL = 1, Course Adj = 1, Tap Select = 0
- */
- volatile ccsr_gur_t *gur =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- out_be32(&gur->ddrdllcr, 0x81000000);
- udelay(200);
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c217c278e..c69dfe4cc 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -39,8 +39,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void);
-
int checkboard (void)
{
u8 vboot;
@@ -74,23 +72,6 @@ int checkboard (void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_SPD_EEPROM
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
#if !defined(CONFIG_SPD_EEPROM)
/*
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 7cb549b1b..e3e830066 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -76,19 +76,6 @@ int checkboard(void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....\n");
-
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 15b46b0da..e54fde253 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size;
}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- dram_size = fixed_sdram();
- set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts("DDR: ");
- return dram_size;
-}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 07b08014d..40589da11 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -44,8 +44,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void);
-
int checkboard(void)
{
u8 sw;
@@ -70,31 +68,6 @@ int checkboard(void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing....");
-
-#ifdef CONFIG_DDR_SPD
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram();
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- dram_size,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- puts(" DDR: ");
- return dram_size;
-}
-
#if !defined(CONFIG_DDR_SPD)
/*
* Fixed sdram init -- doesn't use serial presence detect.
@@ -170,6 +143,13 @@ phys_size_t fixed_sdram(void)
udelay(500);
#endif
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
+ LAW_TRGT_IF_DDR) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 02:21:11 +0000