diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 49 |
1 files changed, 39 insertions, 10 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b9a819375..2e4a06c35 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,12 +37,15 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <linux/compiler.h> #include "mp.h" -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> #include <errno.h> #endif +#include "../../../../drivers/block/fsl_sata.h" + DECLARE_GLOBAL_DATA_PTR; extern void srio_init(void); @@ -301,6 +304,7 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); */ int cpu_init_r(void) { + __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_SYS_LBC_LCRR volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif @@ -316,10 +320,9 @@ int cpu_init_r(void) #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; - uint svr, ver; + uint ver; u32 l2siz_field; - svr = get_svr(); ver = SVR_SOC_VER(svr); asm("msync;isync"); @@ -401,8 +404,8 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + if ((SVR_SOC_VER(svr) == SVR_P2040) || + (SVR_SOC_VER(svr) == SVR_P2040_E)) { puts("N/A\n"); goto skip_l2; } @@ -488,6 +491,32 @@ skip_l2: fman_enet_init(); #endif +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + /* + * For P1022/1013 Rev1.0 silicon, after power on SATA host + * controller is configured in legacy mode instead of the + * expected enterprise mode. Software needs to clear bit[28] + * of HControl register to change to enterprise mode from + * legacy mode. We assume that the controller is offline. + */ + if (IS_SVR_REV(svr, 1, 0) && + ((SVR_SOC_VER(svr) == SVR_P1022) || + (SVR_SOC_VER(svr) == SVR_P1022_E) || + (SVR_SOC_VER(svr) == SVR_P1013) || + (SVR_SOC_VER(svr) == SVR_P1013_E))) { + fsl_sata_reg_t *reg; + + /* first SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + + /* second SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + } +#endif + + return 0; } @@ -523,17 +552,17 @@ void cpu_secondary_init_r(void) { #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ -#ifdef CONFIG_SYS_QE_FW_IN_NAND +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; - size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; /* load QE firmware from NAND flash to DDR first */ - ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", - CONFIG_SYS_QE_FW_IN_NAND, ret); + CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); } #endif qe_init(qe_base); |