diff options
| -rw-r--r-- | board/freescale/mpc8610hpcd/mpc8610hpcd.c | 4 | ||||
| -rw-r--r-- | board/freescale/mpc8641hpcn/mpc8641hpcn.c | 6 | ||||
| -rw-r--r-- | board/sbc8641d/sbc8641d.c | 12 | ||||
| -rw-r--r-- | cpu/mpc86xx/ddr-8641.c | 4 | ||||
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 4 |
5 files changed, 15 insertions, 15 deletions
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index a85ebead5..419b2c191 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -154,7 +154,7 @@ phys_size_t fixed_sdram(void) ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode_1 = 0x00480432; + ddr->sdram_mode = 0x00480432; ddr->sdram_mode_2 = 0x00000000; ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ ddr->sdram_data_init = 0xDEADBEEF; @@ -170,7 +170,7 @@ phys_size_t fixed_sdram(void) udelay(500); - ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ + ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 441127bbf..ce2632078 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -101,7 +101,7 @@ fixed_sdram(void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; @@ -119,9 +119,9 @@ fixed_sdram(void) #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #endif asm("sync; isync"); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index c39d2c020..f118a6eaa 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -127,9 +127,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; @@ -140,7 +140,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; asm ("sync; isync"); udelay (500); @@ -158,9 +158,9 @@ long int fixed_sdram (void) ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; @@ -171,7 +171,7 @@ long int fixed_sdram (void) udelay (500); - ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; + ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; asm ("sync; isync"); udelay (500); diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index 51d0102ce..b8f2c9387 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); @@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync"); - out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg); + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); /* * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index a8398348b..fdfc654f2 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -114,9 +114,9 @@ typedef struct ccsr_ddr { uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */ + uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ + uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ |