diff options
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/cpu.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/ehci.h (renamed from arch/arm/include/asm/arch-exynos/ehci-s5p.h) | 10 | ||||
| -rw-r--r-- | drivers/usb/host/Makefile | 2 | ||||
| -rw-r--r-- | drivers/usb/host/ehci-exynos.c (renamed from drivers/usb/host/ehci-s5p.c) | 18 |
4 files changed, 18 insertions, 15 deletions
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index b1e22f2c1..dee039df9 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -46,6 +46,7 @@ #define EXYNOS4_USBOTG_BASE 0x12480000 #define EXYNOS4_MMC_BASE 0x12510000 #define EXYNOS4_SROMC_BASE 0x12570000 +#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 #define EXYNOS4_ADC_BASE 0x13910000 @@ -69,6 +70,7 @@ #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 +#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 #define EXYNOS5_MMC_BASE 0x12200000 #define EXYNOS5_SROMC_BASE 0x12250000 #define EXYNOS5_USBOTG_BASE 0x12480000 @@ -159,6 +161,7 @@ SAMSUNG_BASE(swreset, SWRESET) SAMSUNG_BASE(timer, PWMTIMER_BASE) SAMSUNG_BASE(uart, UART_BASE) SAMSUNG_BASE(usb_phy, USBPHY_BASE) +SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) SAMSUNG_BASE(usb_otg, USBOTG_BASE) SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci.h index 68feb85ed..8aeff8ab2 100644 --- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -1,5 +1,5 @@ /* - * SAMSUNG S5P USB HOST EHCI Controller + * SAMSUNG EXYNOS USB HOST EHCI Controller * * Copyright (C) 2012 Samsung Electronics Co.Ltd * Vivek Gautam <gautam.vivek@samsung.com> @@ -20,8 +20,8 @@ * MA 02110-1301 USA */ -#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ -#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ +#ifndef __ASM_ARM_ARCH_EHCI_H__ +#define __ASM_ARM_ARCH_EHCI_H__ #define CLK_24MHZ 5 @@ -43,7 +43,7 @@ #define EHCICTRL_ENAINCR16 (1 << 26) /* Register map for PHY control */ -struct s5p_usb_phy { +struct exynos_usb_phy { unsigned int usbphyctrl0; unsigned int usbphytune0; unsigned int reserved1[2]; @@ -63,4 +63,4 @@ struct s5p_usb_phy { /* Switch on the VBUS power. */ int board_usb_vbus_init(void); -#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ +#endif /* __ASM_ARM_ARCH_EHCI_H__ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 4547f3782..6de91640d 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -42,6 +42,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o else COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif +COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o @@ -51,7 +52,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o -COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-exynos.c index 4dd4ec168..3830c43b8 100644 --- a/drivers/usb/host/ehci-s5p.c +++ b/drivers/usb/host/ehci-exynos.c @@ -1,5 +1,5 @@ /* - * SAMSUNG S5P USB HOST EHCI Controller + * SAMSUNG EXYNOS USB HOST EHCI Controller * * Copyright (C) 2012 Samsung Electronics Co.Ltd * Vivek Gautam <gautam.vivek@samsung.com> @@ -23,12 +23,12 @@ #include <common.h> #include <usb.h> #include <asm/arch/cpu.h> -#include <asm/arch/ehci-s5p.h> +#include <asm/arch/ehci.h> #include "ehci.h" #include "ehci-core.h" /* Setup the EHCI host controller. */ -static void setup_usb_phy(struct s5p_usb_phy *usb) +static void setup_usb_phy(struct exynos_usb_phy *usb) { clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | @@ -61,7 +61,7 @@ static void setup_usb_phy(struct s5p_usb_phy *usb) } /* Reset the EHCI host controller. */ -static void reset_usb_phy(struct s5p_usb_phy *usb) +static void reset_usb_phy(struct exynos_usb_phy *usb) { /* HOST_PHY reset */ setbits_le32(&usb->usbphyctrl0, @@ -79,12 +79,12 @@ static void reset_usb_phy(struct s5p_usb_phy *usb) */ int ehci_hcd_init(void) { - struct s5p_usb_phy *usb; + struct exynos_usb_phy *usb; - usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); setup_usb_phy(usb); - hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE); + hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci(); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); @@ -101,9 +101,9 @@ int ehci_hcd_init(void) */ int ehci_hcd_stop() { - struct s5p_usb_phy *usb; + struct exynos_usb_phy *usb; - usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); reset_usb_phy(usb); return 0; |