esd config files updated

author: stroese <stroese> 2004-12-16 18:05:42 +0000
committer: stroese <stroese> 2004-12-16 18:05:42 +0000
commit: a20b27a36b7b1f593e18b4efd506e5f01a392dc6 (patch)
tree: f9dc45c287966bb96c38a8267d07b217727efb3c /include
parent: 44acc8d334a8b9ddb81fc238b094574991f19afa (diff)
download: olio-uboot-2014.01-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.xz
olio-uboot-2014.01-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.zip
25 files changed, 3659 insertions, 264 deletions
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
index 5a62139f9..8d21b3f18 100644
--- a/include/configs/ADCIOP.h
+++ b/include/configs/ADCIOP.h
@@ -155,7 +155,7 @@
 #define CFG_ENV_SIZE		0x0400		/* Size of Environment vars	*/
 #define CFG_ENV_ADDR		\
 	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x7800		/* Offset for VxWorks eth-addr	*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
 
 #else /* Use FLASH for environment variables */
 
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
new file mode 100644
index 000000000..588f9f601
--- /dev/null
+++ b/include/configs/APC405.h
@@ -0,0 +1,384 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_APCG405		1	/* ...on a APC405 board 	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND							\
+	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
+	"bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND							\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
+	"bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#if 1 /* test-only */
+#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#else
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#endif
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define	CFG_ATA_BASE_ADDR	0xF0100000
+#define	CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFF80000
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
+                                        /* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
+#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define DUART0_BA       0xF0000400          /* DUART Base Address               */
+#define DUART1_BA       0xF0000408          /* DUART Base Address               */
+#define RTC_BA          0xF0000500          /* RTC Base Address                 */
+#define PS2_BA          0xF0000600          /* PS/2 Base Address                */
+#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
+#define FPGA_BA         0xF0100100          /* FPGA internal Base Address       */
+#define FUJI_BA         0xF0100200          /* Fuji internal Base Address       */
+#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address       */
+#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address       */
+#define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
+
+#define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address       */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                                  */
+#define CFG_EBC_PB0AP   0x92015480
+#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (Flash Bank 1) initialization                                  */
+#define CFG_EBC_PB1AP   0x92015480
+#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
+#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
+#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
+#define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 5 (Epson VGA) initialization                                     */
+#define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
+#define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL           0x008
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_CF_RESET  0x0001
+#define CFG_FPGA_CTRL_WDI       0x0002
+#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+
+#define CONFIG_LCD_BIG          2           /* Epson S1D13806 used              */
+
+/* Image information... */
+#define CONFIG_LCD_USED         CONFIG_LCD_BIG
+#define CFG_LCD_HEADER_NAME     "s1d13806_640_480_16bpp.h"
+#define CFG_LCD_LOGO_NAME       "logo_640_480_24bpp.c"
+
+#define CFG_LCD_MEM             CFG_LCD_BIG_MEM
+#define CFG_LCD_REG             CFG_LCD_BIG_REG
+
+#define CFG_LCD_LOGO_MAX_SIZE   (1024*1024)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index f226a51df..dfa62200e 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -106,6 +106,8 @@
 #define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
@@ -139,6 +141,8 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
@@ -190,10 +194,12 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
-#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
+#define CFG_ENV_ADDR		0xFFFB0000	/* Address of Environment Sector*/
 #define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+#define CFG_ENV_SIZE		0x04000	        /* Size of Environment 	        */
+
+#define CFG_ENV_ADDR_REDUND     0xFFFA0000
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 7ed01d16d..8e3f34f98 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -40,27 +40,24 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -164,6 +161,9 @@
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 7c600d92e..b159182eb 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -44,30 +44,17 @@
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
-#if 0
-#define CONFIG_PREBOOT								\
-	"crc32 f0207004 ffc 0;"							\
-	"if cmp 0 f0207000 1;"							\
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
-	"else;echo Old CRC is bad;fi"
-#endif
-
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_DNS | \
@@ -79,6 +66,7 @@
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_EEPROM	)
@@ -86,6 +74,8 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_SUPPORT_VFAT
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -134,35 +124,39 @@
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
 
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -221,23 +215,24 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
 #if 1 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 #define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CFG_ENV_ADDR		\
 	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE		0x200	/* 512 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 6ee5698a1..4bb47c324 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001-2003
+ * (C) Copyright 2001-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -40,35 +40,22 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
-#if 0
-#define CONFIG_PREBOOT								\
-	"crc32 f0207004 ffc 0;"							\
-	"if cmp 0 f0207000 1;"							\
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
-	"else;echo Old CRC is bad;fi"
-#endif
-
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
@@ -82,17 +69,34 @@
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_JFFS2	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
 				CFG_CMD_EEPROM	)
 
+#if 0 /* test-only */
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
+#endif
+#endif
+
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_SUPPORT_VFAT
+
+#if 0 /* test-only */
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#endif
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -124,6 +128,8 @@
 
 #define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
@@ -141,6 +147,8 @@
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
@@ -151,29 +159,31 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
 
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -254,7 +264,7 @@
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 3c94ebc34..dee26f871 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -41,27 +41,22 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
-#if 0
-#define CONFIG_PREBOOT								\
-	"crc32 f0207004 ffc 0;"							\
-	"if cmp 0 f0207000 1;"							\
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
-	"else;echo Old CRC is bad;fi"
-#endif
-
 #undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* default boot command */
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
@@ -75,6 +70,7 @@
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_JFFS2	| \
@@ -86,6 +82,8 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_SUPPORT_VFAT
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -155,6 +153,8 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
 #define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
@@ -232,13 +232,14 @@
  * I2C EEPROM (CAT24WC32) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
 #define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
 #define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
 					/* 32 byte page write mode using*/
 					/* last 5 bits of the address	*/
@@ -254,7 +255,7 @@
 
 #define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -331,16 +332,20 @@
 #define CFG_FPGA_MODE_CF_RESET	    0x0001
 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
-#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+#define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
+#define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
+#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
+#define CFG_FPGA_MODE_1WIRE         0x1000
+#define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
+#define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000
 
 /* FPGA Status Reg */
-#define CFG_FPGA_STATUS_DIP0	0x0001
-#define CFG_FPGA_STATUS_DIP1	0x0002
-#define CFG_FPGA_STATUS_DIP2	0x0004
-#define CFG_FPGA_STATUS_FLASH	0x0008
-#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+#define CFG_FPGA_STATUS_DIP0    0x0001
+#define CFG_FPGA_STATUS_DIP1    0x0002
+#define CFG_FPGA_STATUS_DIP2    0x0004
+#define CFG_FPGA_STATUS_FLASH   0x0008
+#define CFG_FPGA_STATUS_1WIRE   0x1000
+#define CFG_FPGA_STATUS_SIM_OK  0x2000
 
 #define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
 #define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
new file mode 100644
index 000000000..5c4259df3
--- /dev/null
+++ b/include/configs/CPCI405DT.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+#if 0 /* test-only */
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
+#endif
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if special string is typed */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#undef  CONFIG_AUTOBOOT_STOP_STR        /* defined via environment var  */
+#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
+#define CFG_FPGA_MODE_DUART_RESET   0x0002
+#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
index 3e0cee402..efb27cc61 100644
--- a/include/configs/CPCI440.h
+++ b/include/configs/CPCI440.h
@@ -35,7 +35,7 @@
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
 #undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -43,7 +43,11 @@
  *----------------------------------------------------------------------*/
 #define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
 #define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#if 1
 #define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#else
+#define CFG_MONITOR_BASE    0x01fc0000	    /* start of monitor		*/
+#endif
 #define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
 #define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
 
@@ -154,16 +158,17 @@
 
 #endif
 
-#define CONFIG_BOOTARGS		"root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
-#define CONFIG_BOOTDELAY	-1		    /* disable autoboot */
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 #define CONFIG_BAUDRATE		9600
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #if 0 /* test-only */
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
new file mode 100644
index 000000000..45fcee00f
--- /dev/null
+++ b/include/configs/CPCI750.h
@@ -0,0 +1,602 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/*************************************************************************
+ * (c) 2004 esd gmbh Hannover
+ *
+ *
+ * from db64360.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+  ************************************************************************/
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/processor.h>
+
+/* This define must be before the core.h include */
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#ifndef __ASSEMBLY__
+#include <../board/Marvell/include/core.h>
+#endif
+/*-----------------------------------------------------*/
+
+#include "../board/esd/cpci750/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_750FX			/* we have a 750FX (override local.h) */
+
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#define CONFIG_BAUDRATE		9600 	/* console baudrate = 9600	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CFG_BOARD_NAME		"CPCI750"
+#define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
+
+/*#define CFG_HUSH_PARSER*/
+#undef CFG_HUSH_PARSER
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/* Define which ETH port will be used for connecting the network */
+#define CFG_ETH_PORT		ETH_0
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CONFIG_NET_MULTI
+#define MV_ETH_DEVS             1
+#define CONFIG_ETHER_PORT	0
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot disabled		*/
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+
+/* -----------------------------------------------------------------------------
+ * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
+ */
+
+#define CONFIG_IPADDR		"192.168.0.185"
+
+#define CONFIG_SERIAL		"AA000001"
+#define CONFIG_SERVERIP		"10.0.0.79"
+#define CONFIG_ROOTPATH	        "/export/nfs_cpci750/%s"
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS  n
+#define CONFIG_TESETDRAMWALK	n
+
+/* ----------------------------------------------------------------------------- */
+
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL    \
+			 | CFG_CMD_ASKENV  \
+			 | CFG_CMD_I2C     \
+			 | CFG_CMD_CACHE   \
+			 | CFG_CMD_EEPROM  \
+			 | CFG_CMD_PCI     \
+			 | CFG_CMD_ELF	   \
+			 | CFG_CMD_DATE	   \
+                         | CFG_CMD_NET     \
+                         | CFG_CMD_PING    \
+                         | CFG_CMD_IDE     \
+                         | CFG_CMD_FAT     \
+                         | CFG_CMD_EXT2    \
+					)
+
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_SPEED   80000		/* I2C speed default */
+
+#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CFG_MEMTEST_START	0x00400000*/	/* memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+/*#define CFG_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM	*/
+
+/*
+#define CFG_DRAM_TEST
+ * DRAM tests
+ *   CFG_DRAM_TEST - enables the following tests.
+ *
+ *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *                        Environment variable 'test_dram_data' must be
+ *                        set to 'y'.
+ *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *                        addressable. Environment variable
+ *                        'test_dram_address' must be set to 'y'.
+ *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *                        This test takes about 6 minutes to test 64 MB.
+ *                        Environment variable 'test_dram_walk' must be
+ *                        set to 'y'.
+ */
+#define CFG_DRAM_TEST
+#if defined(CFG_DRAM_TEST)
+#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM	*/
+#define CFG_DRAM_TEST_DATA
+#define CFG_DRAM_TEST_ADDRESS
+#define CFG_DRAM_TEST_WALK
+#endif /* CFG_DRAM_TEST */
+
+#define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)	 	*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_TCLK		133000000
+
+/*#define CFG_750FX_HID0		0x8000c084*/
+#define CFG_750FX_HID0		0x80008484
+#define CFG_750FX_HID1		0x54800000
+#define CFG_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+ /*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#undef    CFG_INIT_RAM_LOCK
+/* #define CFG_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
+/* #define CFG_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
+#define CFG_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+/*#define CFG_INTERNAL_RAM_ADDR	0xfba00000*/
+#define CFG_INTERNAL_RAM_ADDR	0xf1080000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define	CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define	CFG_SDRAM2_BASE		0x20000000
+#define	CFG_SDRAM3_BASE		0x30000000
+#define	CFG_SDRAM4_BASE		0x40000000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	0xfff00000
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+
+#define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	   /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* there is only one bank		*/
+#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xfc000000 /* start of flash banks              */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the cpci750 Board :                      */
+/* GT-Chipset Register Area                            */
+/* GT-Chipset internal SRAM 256k                       */
+/* SRAM on external device module                      */
+/* Real time clock on external device module           */
+/* dobble UART on external device module               */
+/* Data flash on external device module                */
+/* Boot flash on external device module                */
+/*******************************************************/
+#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define  CFG_CPCI750_RESET_ADDR	0x14000000				/* After power on Reset the CPCI750 is here */
+
+#undef 	MARVEL_STANDARD_CFG
+#ifndef 	MARVEL_STANDARD_CFG
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+/*#define CFG_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
+#define CFG_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
+
+#define CFG_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
+#define CFG_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
+#define CFG_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
+#define CFG_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
+#define CFG_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
+
+#define CFG_BOOT_SIZE		_16M 					/* cpci750 flash 0     */
+#define CFG_DEV0_SIZE		_16M 					/* cpci750 flash 1     */
+#define CFG_DEV1_SIZE		_16M 					/* cpci750 flash 2     */
+#define CFG_DEV2_SIZE		_16M 					/* cpci750 flash 3     */
+#define CFG_DEV3_SIZE		_16M 					/* cpci750 nvram/can   */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#endif
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CFG_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV3_PAR		0x8FCFFFFF				/* nvram/can    */
+#define CFG_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
+
+        /*   c    4    a      8     2     4    1      c		*/
+        /* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
+        /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+        /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+        /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* MPP Control MV64360 Appendix P P. 632*/
+#define CFG_MPP_CONTROL_0	0x00002222	/*                                   */
+#define CFG_MPP_CONTROL_1	0x11110000	/*                                   */
+#define CFG_MPP_CONTROL_2	0x11111111	/*                                   */
+#define CFG_MPP_CONTROL_3	0x00001111     	/*                                   */
+/* #define CFG_SERIAL_PORT_MUX	0x00000102*/	/*                                   */
+
+
+#define CFG_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
+
+/* setup new config_value for MV64360 DDR-RAM To_do !! */
+/*# define CFG_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
+/*# define CFG_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
+				/* GB has high prio.
+				   idma has low prio
+				   MPSC has low prio
+				   pci has low prio 1 and 2
+				   cpu has high prio
+				   Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
+				   ECC disable
+				   non registered DRAM */
+				/* 31:26   25:22  21:20 19 18 17 16 */
+				/* 100001 0000   010   0   0   0  0 */
+				/* refresh_count=0x400
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 0  1  0x400 */
+# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+#if defined (CONFIG_750CX)
+#define CFG_PCI_IDSEL 0x0
+#else
+#define CFG_PCI_IDSEL 0x30
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET                /* no reset for ide supported   */
+#define CONFIG_IDE_PREINIT              /* check for units              */
+
+#define CFG_IDE_MAXBUS          2               /* max. 1 IDE busses    */
+#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR       0
+#define CFG_ATA_IDE0_OFFSET     0
+#define CFG_ATA_IDE1_OFFSET     0
+
+#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
+#define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
+#define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
+
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
+ * IBAT4 and DBAT4
+ * FIXME: ingo disable BATs for Linux Kernel
+ */
+#undef SETUP_HIGH_BATS_FX750		/* don't initialize BATS 4-7 */
+/*#define SETUP_HIGH_BATS_FX750*/		/* initialize BATS 4-7 */
+
+#ifdef SETUP_HIGH_BATS_FX750
+#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT5U CFG_IBAT5U
+
+/* IBAT6 and DBAT6 */
+#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U CFG_IBAT6U
+
+/* IBAT7 and DBAT7 */
+#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U CFG_IBAT7U
+
+#else		/* set em out of range for Linux !!!!!!!!!!! */
+#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT5U CFG_IBAT4U
+
+/* IBAT6 and DBAT6 */
+#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U CFG_IBAT4U
+
+/* IBAT7 and DBAT7 */
+#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U CFG_IBAT4U
+
+#endif
+/* FIXME: ingo end: disable BATs for Linux Kernel */
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x51
+#define DIMM1_I2C_ADDR	0x52
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+
+#if 0
+#define	CFG_ENV_IS_IN_FLASH	0
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+#endif
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CFG_I2C_EEPROM_ADDR     0x050
+#define CFG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
+
+#define CFG_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+/*#define CFG_L2*/
+#undef CFG_L2
+
+/*    #ifdef CONFIG_750CX*/
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT      1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 1aff9e47c..ae54683b9 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -52,6 +52,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 666a0d0ff..6bebaaa76 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -40,23 +40,16 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
@@ -81,6 +74,8 @@
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
+#define CONFIG_PRAM		2	/* reserve 2 kB "protected RAM" */
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index 5a5415a13..b9170925a 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -47,17 +47,21 @@
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND	"bootm fff00000"
 
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_EEPROM	)
 
@@ -107,6 +111,8 @@
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
new file mode 100644
index 000000000..df4ed3902
--- /dev/null
+++ b/include/configs/G2000.h
@@ -0,0 +1,425 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_G2000		1	/* ...on a PLU405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE		115200
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_PREBOOT
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off\0"				\
+	"addmisc=setenv bootargs $(bootargs) "				\
+		"console=ttyS0,$(baudrate) "				\
+		"panic=1\0"						\
+	"flash_nfs=run nfsargs addip addmisc;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip addmisc;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);"				\
+		"run nfsargs addip addmisc;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/g2000/pImage\0"				\
+	"kernel_addr=ff800000\0"				        \
+	"ramdisk_addr=ff900000\0"				        \
+	"pciconfighost=yes\0"				                \
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
+
+#if 0 /* test-only */
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if 0 /* test-only */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*----------------------------------------------------------------------------*/
+/* adding Ethernet setting:  FTS OUI 00:11:0B */
+/*----------------------------------------------------------------------------*/
+#define CONFIG_ETHADDR          00:11:0B:00:00:01
+#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
+#define CONFIG_IPADDR		10.48.8.178
+#define CONFIG_IP1ADDR		10.48.8.188
+#define CONFIG_NETMASK		255.255.255.128
+#define CONFIG_SERVERIP		10.48.8.138
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR	0x68
+
+#if 0 /* test-only */
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if 0 /* APC405 */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#else /* G2000 */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#endif
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFFC0000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#else	/* DEFAULT: environment in flash, using redundand flash sectors */
+
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_ENV_ADDR		0xFFFA0000 /* environment starts before u-boot */
+#define CFG_ENV_SECT_SIZE	0x20000	/* 128k bytes may be used for env vars*/
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Intel Strata Flash) initialization                            */
+#define CFG_EBC_PB0AP   0x92015480
+#define CFG_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 ( Power TAU) initialization               */
+/* #define CFG_EBC_PB1AP           0x04041000 */
+/* #define CFG_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB1AP           0x00000000
+#define CFG_EBC_PB1CR           0x00000000
+
+/* Memory Bank 2 (Intel Flash) initialization                 */
+#define CFG_EBC_PB2AP           0x00000000
+#define CFG_EBC_PB2CR           0x00000000
+
+/* Memory Bank 3 (NAND) initialization                        */
+#define CFG_EBC_PB3AP           0x92015480
+#define CFG_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
+
+/* Memory Bank 4 (FPGA regs) initialization                                     */
+#define CFG_EBC_PB4AP           0x00000000
+#define CFG_EBC_PB4CR           0x00000000  /* leave it blank  */
+
+#define CFG_NAND_BASE   0xF4000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ *
+ * following GPIO setting changed for G20000, 080304
+ */
+#define CFG_GPIO0_OSRH          0x40005555
+#define CFG_GPIO0_OSRL          0x40000110
+#define CFG_GPIO0_ISR1H         0x00000000
+#define CFG_GPIO0_ISR1L         0x15555445
+#define CFG_GPIO0_TSRH          0x00000000
+#define CFG_GPIO0_TSRL          0x00000000
+#define CFG_GPIO0_TCR           0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_66_33_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_66_33_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
new file mode 100644
index 000000000..828592b05
--- /dev/null
+++ b/include/configs/HH405.h
@@ -0,0 +1,481 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_HH405		1	/* ...on a HH405 board 	        */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT	        "autoupd"
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define	CFG_ATA_BASE_ADDR	0xF0100000
+#define	CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#if 0 /* test-only */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#else
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#endif
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#if 1 /* test-only */
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#else
+/* CAT24WC32/64... */
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last	5 bits of the address	*/
+#endif
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
+					/* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
+#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
+#define CFG_EBC_PB0AP           0x92015480
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (Epson LCD) initialization                                     */
+#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+#define CFG_LCD_LOGO_MAX_SIZE   (1024*1024)
+
+/*-----------------------------------------------------------------------
+ * Universal Interrupt Controller (UIC) Setup
+ */
+
+/*
+ * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
+ */
+#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_EXT6)
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL           0x000
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_REV0      0x0001
+#define CFG_FPGA_CTRL_REV1      0x0002
+#define CFG_FPGA_CTRL_VGA0_BL   0x0004
+#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define CFG_FPGA_CTRL_CF_RESET  0x0040
+#define CFG_FPGA_CTRL_PS2_PWR   0x0080
+#define CFG_FPGA_CTRL_CF_PWR    0x0100      /* low active                    */
+#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
+#define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
+
+#define LCD_CLK_OFF             0x0000      /* Off                           */
+#define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
+#define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
+#define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
+#define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
+#define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
+#define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
+#define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555440
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0017
+
+#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
+#define CFG_TOUCH_RST		(0x80000000 >> 9)
+#define CFG_LCD0_RST		(0x80000000 >> 30)
+#define CFG_LCD1_RST		(0x80000000 >> 31)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index ff0d8d08c..57212e0f6 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -35,32 +35,28 @@
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_HUB405		1	/* ...on a ASH405 board		*/
+#define CONFIG_HUB405		1	/* ...on a HUB405 board		*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
@@ -127,6 +123,11 @@
 
 #define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
+
 /*-----------------------------------------------------------------------
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
@@ -160,6 +161,8 @@
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -352,7 +355,11 @@
 #define CFG_GPIO0_TSRL		0x00000000
 #define CFG_GPIO0_TCR		0xF7FE0014
 
-#define CFG_DUART_RST		(0x80000000 >> 14)
+#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_UART2_RS232         (0x80000000 >> 5)
+#define CFG_UART3_RS232         (0x80000000 >> 6)
+#define CFG_UART4_RS232         (0x80000000 >> 7)
+#define CFG_UART5_RS232         (0x80000000 >> 8)
 
 /*
  * Internal Definitions
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index c88d882e0..4a629e099 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -52,6 +52,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -121,7 +122,7 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
 #define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
@@ -270,7 +271,7 @@
 #define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_ETHERNET_MAC_ADDR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 3dcb514fa..4cc67bce2 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -52,6 +52,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -268,7 +269,7 @@
 #define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_ETHERNET_MAC_ADDR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 49fdfddda..26711257c 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -42,27 +42,21 @@
 
 #define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-#if 0
-#define CONFIG_PREBOOT								\
-	"crc32 f0207004 ffc 0;"							\
-	"if cmp 0 f0207000 1;"							\
-	"then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"		\
-	"else;echo Old CRC is bad;fi"
-#endif
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#if 1
-#define CONFIG_BOOTCOMMAND							\
-	"bootm fffc0000"
-#else
-#define CONFIG_BOOTCOMMAND							\
-	"mw.l 0 ffffffff; mw.l 4 ffffffff;"					\
-	"while cmp 0 4 1; do echo Waiting for Host...;done;"			\
-	"bootm 400000"
-#endif
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"mem_linux=14336k\0"					        \
+	"optargs=panic=0\0"					        \
+	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
+	"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+	""
+#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcon;loadpci"
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
@@ -321,16 +315,33 @@
 #define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
 #define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
 #define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
+#define CFG_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
+#if 0 /* test-only */
 #define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
 #define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
 #define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#endif
 
 /*
  * Internal Definitions
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 0798af4d0..73a788543 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -40,33 +40,37 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND "bootm fff00000"
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+#if 0 /* test-only */
+#define CONFIG_NET_MULTI	1
+
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
+#else
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#endif
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_NAND	| \
 				CFG_CMD_DATE	| \
@@ -78,6 +82,11 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -112,6 +121,8 @@
 
 #define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
@@ -131,6 +142,15 @@
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
@@ -169,30 +189,34 @@
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
 
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 49414bb29..bf561ee6e 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001-2003
+ * (C) Copyright 2001-2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -40,27 +40,22 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_BSP	| \
@@ -72,7 +67,8 @@
 				CFG_CMD_MII	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_EEPROM	)
+				CFG_CMD_UNIVERSE | \
+				CFG_CMD_EEPROM  )
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -82,8 +78,8 @@
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR	 0xF0000300 /* RTC Base Address		*/
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
@@ -111,6 +107,8 @@
 
 #define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
@@ -128,6 +126,8 @@
 
 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
@@ -138,26 +138,30 @@
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
 
-#undef CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408	/* PCI Device ID: PMC-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -268,6 +272,8 @@
 #define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
 #define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
new file mode 100644
index 000000000..2d52a8b50
--- /dev/null
+++ b/include/configs/TASREG.h
@@ -0,0 +1,278 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _TASREG_H
+#define _TASREG_H
+
+#ifndef __ASSEMBLY__
+#include <asm/m5249.h>
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5249			/* define processor type */
+
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM	              /* no pre-loader required!!! ;-) */
+
+#define CONFIG_COMMANDS	      ((CONFIG_CMD_DFL        |    \
+                                CFG_CMD_BSP           |    \
+                                CFG_CMD_EEPROM        |    \
+                                CFG_CMD_I2C            ) & \
+			       ~(CFG_CMD_NET))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#define CONFIG_BOOTDELAY	3
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+
+#define CFG_LOAD_ADDR	        0x200000	/* default load address */
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#if 0 /* this setting will run the cpu at 11MHz */
+#define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
+#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CFG_CLK		        11289600         /* PLL bypass                  */
+#endif
+
+#if 0 /* this setting will run the cpu at 70MHz */
+#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
+#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CFG_CLK		        72185018         /* The next lower speed        */
+#endif
+
+#if 1 /* this setting will run the cpu at 140MHz */
+#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
+#define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
+#define	CFG_CLK		        132025600        /* MCF5249 can run at 140MHz   */
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define	CFG_MBAR2	        0x80000000
+
+/*-----------------------------------------------------------------------
+ * I2C
+ */
+#define	CONFIG_SOFT_I2C
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#if defined (CONFIG_SOFT_I2C)
+#if 0 /* push-pull */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
+#define	I2C_SCL(x)	{if(x)OUT0|=SCL;else OUT0&=~SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#else /* open-collector */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
+#define	I2C_SCL(x)	{if(x)DIR0&=~SCL;else DIR0|=SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CFG_FLASH_BASE		0xffc00000
+
+#if 0 /* test-only */
+#define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CFG_CSAR0               0xffc0
+#define	CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CFG_CSAR1               0xe000
+#define	CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
+#define	CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
+#define	CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
+#define	CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
+#define	CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
+#define	CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
+
+#define CFG_GPIO1_LED           0x00400000      /* user led                     */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
+
+#endif	/* _TASREG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index b64611bb8..d8370ed66 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -40,33 +40,30 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
-#define CONFIG_SYS_CLK_FREQ	33333334 /* external frequency to pll	*/
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
 
 #define CONFIG_BAUDRATE		9600
 #define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000 ffca0000"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
-	"bootm ffc00000"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_NAND	| \
 				CFG_CMD_DATE	| \
@@ -78,6 +75,8 @@
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_SUPPORT_VFAT
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
@@ -112,13 +111,15 @@
 
 #define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
-#undef CONFIG_UART1_CONSOLE	       /* define for uart1 as console  */
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 
 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE	\
@@ -169,30 +170,34 @@
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
 
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -256,10 +261,10 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_FLASH_BASE		0xFFF80000
 #define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
 
 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CFG_RAMBOOT		1
@@ -349,6 +354,17 @@
 #define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+#define CFG_LCD_LOGO_MAX_SIZE   (1024*1024)
+
+/*-----------------------------------------------------------------------
  * FPGA stuff
  */
 
@@ -398,17 +414,20 @@
  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  * GPIO0[24-27] - UART0 control signal inputs/outputs
  * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
  */
 #define CFG_GPIO0_OSRH		0x40000550
 #define CFG_GPIO0_OSRL		0x00000110
 #define CFG_GPIO0_ISR1H		0x00000000
-#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_ISR1L		0x15555440
 #define CFG_GPIO0_TSRH		0x00000000
 #define CFG_GPIO0_TSRL		0x00000000
-#define CFG_GPIO0_TCR		0xF7FE0014
+#define CFG_GPIO0_TCR		0xF7FE0017
 
 #define CFG_DUART_RST		(0x80000000 >> 14)
+#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
+#define CFG_LCD0_RST		(0x80000000 >> 30)
+#define CFG_LCD1_RST		(0x80000000 >> 31)
 
 /*
  * Internal Definitions
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
new file mode 100644
index 000000000..4aade443f
--- /dev/null
+++ b/include/configs/VOM405.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#undef  CONFIG_PRAM			/* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
+#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
new file mode 100644
index 000000000..b4dfdf4b2
--- /dev/null
+++ b/include/configs/WUH405.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_WUH405		1	/* ...on a WUH405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CFG_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
+
+#define CFG_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
author	stroese <stroese>	2004-12-16 18:05:42 +0000
committer	stroese <stroese>	2004-12-16 18:05:42 +0000
commit	a20b27a36b7b1f593e18b4efd506e5f01a392dc6 (patch)
tree	f9dc45c287966bb96c38a8267d07b217727efb3c /include
parent	44acc8d334a8b9ddb81fc238b094574991f19afa (diff)
download	olio-uboot-2014.01-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.xz olio-uboot-2014.01-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.zip