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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-01-14 17:00:02 +0100 | 
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-01-14 17:00:02 +0100 | 
| commit | a17617d6553369ba72c080128ed8d0b0c33dfc89 (patch) | |
| tree | c8903ddc48e628192c56cc95667f702fd1d77c6e /drivers/watchdog/imx_watchdog.c | |
| parent | 1199c377cf14c240b903e351ab02b3b2cd3800c6 (diff) | |
| parent | 11d80af4876b609832856853b63d06a1011bccf1 (diff) | |
| download | olio-uboot-2014.01-a17617d6553369ba72c080128ed8d0b0c33dfc89.tar.xz olio-uboot-2014.01-a17617d6553369ba72c080128ed8d0b0c33dfc89.zip | |
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'drivers/watchdog/imx_watchdog.c')
| -rw-r--r-- | drivers/watchdog/imx_watchdog.c | 66 | 
1 files changed, 66 insertions, 0 deletions
| diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c new file mode 100644 index 000000000..50e602af1 --- /dev/null +++ b/drivers/watchdog/imx_watchdog.c @@ -0,0 +1,66 @@ +/* + * watchdog.c - driver for i.mx on-chip watchdog + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/io.h> +#include <watchdog.h> +#include <asm/arch/imx-regs.h> + +struct watchdog_regs { +	u16	wcr;	/* Control */ +	u16	wsr;	/* Service */ +	u16	wrsr;	/* Reset Status */ +}; + +#define WCR_WDZST	0x01 +#define WCR_WDBG	0x02 +#define WCR_WDE		0x04	/* WDOG enable */ +#define WCR_WDT		0x08 +#define WCR_WDW		0x80 +#define SET_WCR_WT(x)	(x << 8) + +#ifdef CONFIG_IMX_WATCHDOG +void hw_watchdog_reset(void) +{ +	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + +	writew(0x5555, &wdog->wsr); +	writew(0xaaaa, &wdog->wsr); +} + +void hw_watchdog_init(void) +{ +	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; +	u16 timeout; + +	/* +	 * The timer watchdog can be set between +	 * 0.5 and 128 Seconds. If not defined +	 * in configuration file, sets 128 Seconds +	 */ +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 +#endif +	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | +		WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); +	hw_watchdog_reset(); +} +#endif + +void reset_cpu(ulong addr) +{ +	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + +	writew(WCR_WDE, &wdog->wcr); +	writew(0x5555, &wdog->wsr); +	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */ +	while (1) { +		/* +		 * spin for .5 seconds before reset +		 */ +	} +} |