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| author | Markus Klotzbuecher <mk@denx.de> | 2006-03-24 15:43:16 +0100 |
|---|---|---|
| committer | Markus Klotzbücher <mk@pollux.denx.de> | 2006-03-24 15:43:16 +0100 |
| commit | 2770bcb21c82835a5351176e5b2a9221d7fc8ef9 (patch) | |
| tree | 78edf9afc584e1a76d219bd64d260224a84f0d10 /drivers/tsec.h | |
| parent | 0b953ffc653fc5ab3d3fa47abf0dd9b8bd0703f5 (diff) | |
| parent | 05d8dce9d07cf4073ea15fbc448c1ce22b6baf0f (diff) | |
| download | olio-uboot-2014.01-2770bcb21c82835a5351176e5b2a9221d7fc8ef9.tar.xz olio-uboot-2014.01-2770bcb21c82835a5351176e5b2a9221d7fc8ef9.zip | |
Merge with http://www.denx.de/git/u-boot.git
Diffstat (limited to 'drivers/tsec.h')
| -rw-r--r-- | drivers/tsec.h | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/tsec.h b/drivers/tsec.h index c26fcc0e7..b55b2992b 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -124,7 +124,7 @@ /* Cicada 8204 Extended PHY Control Register 1 */ #define MIIM_CIS8204_EPHY_CON 0x17 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 -#define MIIM_CIS8204_EPHYCON_RGMII 0x1000 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 /* Cicada 8204 Serial LED Control Register */ #define MIIM_CIS8204_SLED_CON 0x1b @@ -161,12 +161,22 @@ #define MIIM_DM9161_10BTCSR_INIT 0x7800 /* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 17 /* Status Register 2 */ -#define MIIM_LXT971_SR2_SPEED_MASK 0xf000 -#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ + +/* DP83865 Control register values */ +#define MIIM_DP83865_CR_INIT 0x9200 + +/* DP83865 Link and Auto-Neg Status Register */ +#define MIIM_DP83865_LANR 0x11 +#define MIIM_DP83865_SPD_MASK 0x0018 +#define MIIM_DP83865_SPD_1000 0x0010 +#define MIIM_DP83865_SPD_100 0x0008 +#define MIIM_DP83865_DPX_FULL 0x0002 #define MIIM_READ_COMMAND 0x00000001 |