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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2012-04-23 08:30:50 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:35 +0200 |
| commit | 148ca64f327a89ef77e84756f5d351af33e59b64 (patch) | |
| tree | 9d2c2d1c16ced71cc1396f708739ed44f6e9c43b /drivers/spi/mxs_spi.c | |
| parent | 79cb14ab39f970b85204ab1b2f796b02bb65335d (diff) | |
| download | olio-uboot-2014.01-148ca64f327a89ef77e84756f5d351af33e59b64.tar.xz olio-uboot-2014.01-148ca64f327a89ef77e84756f5d351af33e59b64.zip | |
spi: mxs: Allow other chip selects to work
MXS SSP controller may have up to three chip selects per port: SS0, SS1 and SS2.
Currently only SS0 is supported in the mxs_spi driver.
Allow all the three chip select to work by selecting the desired one
in bits 20 and 21 of the HW_SSP_CTRL0 register.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/spi/mxs_spi.c')
| -rw-r--r-- | drivers/spi/mxs_spi.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index e7237e720..7859536a6 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -34,6 +34,8 @@ #define MXS_SPI_MAX_TIMEOUT 1000000 #define MXS_SPI_PORT_OFFSET 0x2000 +#define MXS_SSP_CHIPSELECT_MASK 0x00300000 +#define MXS_SSP_CHIPSELECT_SHIFT 20 struct mxs_spi_slave { struct spi_slave slave; @@ -65,6 +67,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct mxs_spi_slave *mxs_slave; uint32_t addr; + struct mx28_ssp_regs *ssp_regs; + int reg; if (!spi_cs_is_valid(bus, cs)) { printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); @@ -82,7 +86,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxs_slave->max_khz = max_hz / 1000; mxs_slave->mode = mode; mxs_slave->regs = (struct mx28_ssp_regs *)addr; + ssp_regs = mxs_slave->regs; + reg = readl(&ssp_regs->hw_ssp_ctrl0); + reg &= ~(MXS_SSP_CHIPSELECT_MASK); + reg |= cs << MXS_SSP_CHIPSELECT_SHIFT; + + writel(reg, &ssp_regs->hw_ssp_ctrl0); return &mxs_slave->slave; } |