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| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2011-01-18 17:53:45 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2011-03-16 10:16:34 +0900 |
| commit | 903de461e4519ae073b4c0e967838c220fa5e5b0 (patch) | |
| tree | 9e49145babc60e83860a325be1ce8de229913964 /drivers/net/sh_eth.h | |
| parent | cc1dd33f273f8c96cbd7539b4a2d1d7aa12773cd (diff) | |
| download | olio-uboot-2014.01-903de461e4519ae073b4c0e967838c220fa5e5b0.tar.xz olio-uboot-2014.01-903de461e4519ae073b4c0e967838c220fa5e5b0.zip | |
net: sh_eth: add support for SH7757's ETHER
SH7757 has ETHER and GETHER. This patch supports EHTER only.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/net/sh_eth.h')
| -rw-r--r-- | drivers/net/sh_eth.h | 53 |
1 files changed, 50 insertions, 3 deletions
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index e153849e3..51e5d5b6f 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -1,5 +1,5 @@ /* - * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler. + * sh_eth.h - Driver for Renesas SuperH ethernet controler. * * Copyright (C) 2008 Renesas Solutions Corp. * Copyright (c) 2008 Nobuhiro Iwamatsu @@ -30,7 +30,11 @@ #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000)) /* The ethernet controller needs to use physical addresses */ +#if defined(CONFIG_SH_32BIT) +#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000)) +#else #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000) +#endif /* Number of supported ports */ #define MAX_PORT_NUM 2 @@ -93,6 +97,7 @@ struct sh_eth_dev { }; /* Register Address */ +#ifdef CONFIG_CPU_SH7763 #define BASE_IO_ADDR 0xfee00000 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) @@ -130,6 +135,34 @@ struct sh_eth_dev { #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) +#elif defined(CONFIG_CPU_SH7757) +#define BASE_IO_ADDR 0xfef00000 + +#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) +#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) + +#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) +#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) +#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) +#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) +#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) +#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) +#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) +#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) +#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) +#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) +#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) +#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) +#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) +#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) +#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) +#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) +#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) +#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) +#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) +#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) +#endif + /* * Register's bits * Copy from Linux driver source code @@ -149,6 +182,10 @@ enum DMAC_M_BIT { EDMR_SRST = 0x03, EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ +#elif defined CONFIG_CPU_SH7757 + EDMR_SRST = 0x01, + EMDR_DESC_R = 0x30, /* Descriptor reserve size */ + EDMR_EL = 0x40, /* Litte endian */ #else /* CONFIG_CPU_SH7763 */ EDMR_SRST = 0x01, #endif @@ -287,7 +324,7 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#ifdef CONFIG_CPU_SH7763 +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -317,8 +354,10 @@ enum FELIC_MODE_BIT { #ifdef CONFIG_CPU_SH7763 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) +#elif CONFIG_CPU_SH7757 +#define ECMR_CHG_DM (ECMR_ZPF) #else -#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT) +#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) #endif /* ECSR */ @@ -355,12 +394,20 @@ enum ECSIPR_STATUS_MASK_BIT { /* APR */ enum APR_BIT { +#ifdef CONFIG_CPU_SH7757 + APR_AP = 0x00000001, +#else APR_AP = 0x00000004, +#endif }; /* MPR */ enum MPR_BIT { +#ifdef CONFIG_CPU_SH7757 + MPR_MP = 0x00000001, +#else MPR_MP = 0x00000006, +#endif }; /* TRSCER */ |