diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /drivers/net/ns8382x.c | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
| download | olio-uboot-2014.01-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.xz olio-uboot-2014.01-8ed44d91c8122d00368523b0b746691c895d3b3c.zip | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers/net/ns8382x.c')
| -rw-r--r-- | drivers/net/ns8382x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index a2d61afec..198f73dee 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis) Read and write MII registers using software-generated serial MDIO protocol. See the MII specifications or DP83840A data sheet for details. - The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + The maximum data clock rate is 2.5 MHz. To meet minimum timing we must flush writes to the PCI bus with a PCI read. */ #define mdio_delay(mdio_addr) INL(dev, mdio_addr) |