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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-04-12 22:07:57 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-04-12 22:07:57 +0200 |
| commit | 18122019972ca639ee3b581257e3a63ff7c8efeb (patch) | |
| tree | 52f7223e7c63f43322f3eee4722743e12190a19f /drivers/net/npe/IxEthMii.c | |
| parent | 90639feaa0d66a204f9d03a325ab14e2f97f6cbb (diff) | |
| parent | 785881f775252940185e10fbb2d5299c9ffa6bce (diff) | |
| download | olio-uboot-2014.01-18122019972ca639ee3b581257e3a63ff7c8efeb.tar.xz olio-uboot-2014.01-18122019972ca639ee3b581257e3a63ff7c8efeb.zip | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
drivers/video/exynos_fb.c
Diffstat (limited to 'drivers/net/npe/IxEthMii.c')
| -rw-r--r-- | drivers/net/npe/IxEthMii.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c index 4d92f17ee..f8b439d9d 100644 --- a/drivers/net/npe/IxEthMii.c +++ b/drivers/net/npe/IxEthMii.c @@ -65,7 +65,7 @@ PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; * Scan for PHYs on the MII bus. This function returns * an array of booleans, one for each PHY address. * If a PHY is found at a particular address, the - * corresponding entry in the array is set to TRUE. + * corresponding entry in the array is set to true. * */ @@ -89,7 +89,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) i<IXP425_ETH_ACC_MII_MAX_ADDR; i++) { - phyPresent[i] = FALSE; + phyPresent[i] = false; } /* iterate through the PHY addresses */ @@ -119,7 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) ) { /* supported phy */ - phyPresent[i] = TRUE; + phyPresent[i] = true; } /* end of if(ixEthMiiPhyId) */ else { @@ -131,7 +131,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", ixEthMiiPhyId[i], 2, 3, 4, 5, 6); ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID; - phyPresent[i] = TRUE; + phyPresent[i] = true; } } } @@ -347,10 +347,10 @@ ixEthMiiLinkStatus(UINT32 phyAddr, return IX_FAIL; } - *linkUp = FALSE; - *speed100 = FALSE; - *fullDuplex = FALSE; - *autoneg = FALSE; + *linkUp = false; + *speed100 = false; + *fullDuplex = false; + *autoneg = false; if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) @@ -406,20 +406,20 @@ ixEthMiiLinkStatus(UINT32 phyAddr, if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) { /* 100 Base X full dplx */ - *speed100 = TRUE; - *fullDuplex = TRUE; + *speed100 = true; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) { /* 100 Base X half dplx */ - *speed100 = TRUE; + *speed100 = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) { /* 10 mb full dplx */ - *fullDuplex = TRUE; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) |