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| author | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
| commit | 50bd0057ba8fceeb48533f8b1a652ccd0e170838 (patch) | |
| tree | ea1a183343573c2a48248923b96d316c0956727c /cpu/mpc85xx/cpu.c | |
| parent | 9dbc366744960013965fce8851035b6141f3b3ae (diff) | |
| parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
| download | olio-uboot-2014.01-50bd0057ba8fceeb48533f8b1a652ccd0e170838.tar.xz olio-uboot-2014.01-50bd0057ba8fceeb48533f8b1a652ccd0e170838.zip | |
Merge git://git.denx.de/u-boot into x1
Conflicts:
drivers/usb/usb_ohci.c
Diffstat (limited to 'cpu/mpc85xx/cpu.c')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c057..9c4f21450 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -84,8 +84,9 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif @@ -98,7 +99,12 @@ int checkcpu (void) #endif minor = SVR_MIN(svr); +#if (CONFIG_NUM_CPUS > 1) + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); +#else puts("CPU: "); +#endif cpu = identify_cpu(ver); if (cpu) { @@ -150,11 +156,11 @@ int checkcpu (void) break; } -#if defined(CFG_LBC_LCRR) - lcrr = CFG_LBC_LCRR; +#if defined(CONFIG_SYS_LBC_LCRR) + lcrr = CONFIG_SYS_LBC_LCRR; #else { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } @@ -199,7 +205,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); + rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ udelay(100); } @@ -255,7 +261,7 @@ reset_85xx_watchdog(void) #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; @@ -265,7 +271,7 @@ void dma_init(void) { } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -284,7 +290,7 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -305,7 +311,7 @@ void upmconfig (uint upm, uint * table, uint size) { int i, mdr, mad, old_mad = 0; volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile u32 *brp,*orp; volatile u8* dummy = NULL; int upmmask; |