Merge with http://www.denx.de/git/u-boot.git

1 files changed, 156 insertions, 33 deletions

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 63dcd664b..b4012a8dd 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 
  * Copyright 2004 Freescale Semiconductor.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
@@ -63,13 +66,42 @@ picos_to_clk(int picos)
 	return clks;
 }
 
-unsigned int
-banksize(unsigned char row_dens)
+unsigned int banksize(unsigned char row_dens)
 {
 	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
 }
 
-long int spd_sdram(int(read_spd)(uint addr))
+int read_spd(uint addr)
+{
+	return ((int) addr);
+}
+
+#undef SPD_DEBUG
+#ifdef SPD_DEBUG
+static void spd_debug(spd_eeprom_t *spd)
+{
+	printf ("\nDIMM type:       %-18.18s\n", spd->mpart);
+	printf ("SPD size:        %d\n", spd->info_size);
+	printf ("EEPROM size:     %d\n", 1 << spd->chip_size);
+	printf ("Memory type:     %d\n", spd->mem_type);
+	printf ("Row addr:        %d\n", spd->nrow_addr);
+	printf ("Column addr:     %d\n", spd->ncol_addr);
+	printf ("# of rows:       %d\n", spd->nrows);
+	printf ("Row density:     %d\n", spd->row_dens);
+	printf ("# of banks:      %d\n", spd->nbanks);
+	printf ("Data width:      %d\n",
+			256 * spd->dataw_msb + spd->dataw_lsb);
+	printf ("Chip width:      %d\n", spd->primw);
+	printf ("Refresh rate:    %02X\n", spd->refresh);
+	printf ("CAS latencies:   %02X\n", spd->cas_lat);
+	printf ("Write latencies: %02X\n", spd->write_lat);
+	printf ("tRP:             %d\n", spd->trp);
+	printf ("tRCD:            %d\n", spd->trcd);
+	printf ("\n");
+}
+#endif /* SPD_DEBUG */
+
+long int spd_sdram()
 {
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 	volatile ddr8349_t *ddr = &immap->ddr;
@@ -81,10 +113,10 @@ long int spd_sdram(int(read_spd)(uint addr))
 	unsigned char caslat;
 	unsigned int trfc, trfc_clk, trfc_low;
 
-#warning Current spd_sdram does not fit its usage... adjust implementation or API...
-
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
-
+#ifdef SPD_DEBUG
+	spd_debug(&spd);
+#endif
 	if (spd.nrows > 2) {
 		puts("DDR:Only two chip selects are supported on ADS.\n");
 		return 0;
@@ -219,25 +251,31 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 * Only DDR I is supported
 	 * DDR I and II have different mode-register-set definition
 	 */
-
-	/* burst length is always 4 */
 	switch(caslat) {
 	case 2:
-		ddr->sdram_mode = 0x52; /* 1.5 */
+		tmp = 0x50; /* 1.5 */
 		break;
 	case 3:
-		ddr->sdram_mode = 0x22; /* 2.0 */
+		tmp = 0x20; /* 2.0 */
 		break;
 	case 4:
-		ddr->sdram_mode = 0x62; /* 2.5 */
+		tmp = 0x60; /* 2.5 */
 		break;
 	case 5:
-		ddr->sdram_mode = 0x32; /* 3.0 */
+		tmp = 0x30; /* 3.0 */
 		break;
 	default:
 		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
 		return 0;
 	}
+#if defined (CONFIG_DDR_32BIT)
+	/* set burst length to 8 for 32-bit data path */
+	tmp |= 0x03;
+#else
+	/* set burst length to 4 - default for 64-bit data path */
+	tmp |= 0x02;
+#endif
+	ddr->sdram_mode = tmp;
 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
 	switch(spd.refresh) {
@@ -282,8 +320,13 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 */
 #if defined(CONFIG_DDR_ECC)
 	if (spd.config == 0x02) {
-		ddr->err_disable = 0x0000000d;
-		ddr->err_sbe = 0x00ff0000;
+		/* disable error detection */
+		ddr->err_disable = ~ECC_ERROR_ENABLE;
+
+		/* set single bit error threshold to maximum value,
+		 * reset counter to zero */
+		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+			(0 << ECC_ERROR_MAN_SBEC_SHIFT);
 	}
 	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
 	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
@@ -297,7 +340,8 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
 	 * clock cycle after address/command
 	 */
-	ddr->sdram_clk_cntl = 0x82000000;
+	/*ddr->sdram_clk_cntl = 0x82000000;*/
+	ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
 
 	/*
 	 * Figure out the settings for the sdram_cfg register.  Build up
@@ -311,6 +355,10 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 */
 	tmp = 0xc2000000;
 
+#if defined (CONFIG_DDR_32BIT)
+	/* in 32-Bit mode burst len is 8 beats */
+	tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
 	/*
 	 * sdram_cfg[3] = RD_EN - registered DIMM enable
 	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
@@ -324,7 +372,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 	 * If the user wanted ECC (enabled via sdram_cfg[2])
 	 */
 	if (spd.config == 0x02) {
-		tmp |= 0x20000000;
+		tmp |= SDRAM_CFG_ECC_EN;
 	}
 #endif
 
@@ -340,37 +388,94 @@ long int spd_sdram(int(read_spd)(uint addr))
 	udelay(500);
 
 	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
-
-	return memsize;/*in MBytes*/
+	return memsize; /*in MBytes*/
 }
 #endif /* CONFIG_SPD_EEPROM */
 
 
 #if defined(CONFIG_DDR_ECC)
 /*
- * Initialize all of memory for ECC, then enable errors.
+ * Use timebase counter, get_timer() is not availabe
+ * at this point of initialization yet.
  */
+static __inline__ unsigned long get_tbms (void)
+{
+	unsigned long tbl;
+	unsigned long tbu1, tbu2;
+	unsigned long ms;
+	unsigned long long tmp;
+
+	ulong tbclk = get_tbclk();
+
+	/* get the timebase ticks */
+	do {
+		asm volatile ("mftbu %0":"=r" (tbu1):);
+		asm volatile ("mftb %0":"=r" (tbl):);
+		asm volatile ("mftbu %0":"=r" (tbu2):);
+	} while (tbu1 != tbu2);
+
+	/* convert ticks to ms */
+	tmp = (unsigned long long)(tbu1);
+	tmp = (tmp << 32);
+	tmp += (unsigned long long)(tbl);
+	ms = tmp/(tbclk/1000);
 
-void
-ddr_enable_ecc(unsigned int dram_size)
+	return ms;
+}
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+//#define CONFIG_DDR_ECC_INIT_VIA_DMA
+void ddr_enable_ecc(unsigned int dram_size)
 {
-#ifndef FIXME
-	uint *p = 0;
-	uint i = 0;
+	uint *p;
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+	volatile ddr8349_t *ddr = &immap->ddr;
+	unsigned long t_start, t_end;
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+	uint i;
+#endif
+
+	debug("Initialize a Cachline in DRAM\n");
+	icache_enable();
 
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+	/* Initialise DMA for direct Transfers */
 	dma_init();
+#endif
+
+	t_start = get_tbms();
 
-	for (*p = 0; p < (uint *)(8 * 1024); p++) {
+#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+	debug("DDR init: Cache flush method\n");
+	for (p = 0; p < (uint *)(dram_size); p++) {
 		if (((unsigned int)p & 0x1f) == 0) {
 			ppcDcbz((unsigned long) p);
 		}
+
+		/* write pattern to cache and flush */
 		*p = (unsigned int)0xdeadbeef;
+
 		if (((unsigned int)p & 0x1c) == 0x1c) {
 			ppcDcbf((unsigned long) p);
 		}
 	}
+#else
+	printf("DDR init: DMA method\n");
+	for (p = 0; p < (uint *)(8 * 1024); p++) {
+		/* zero one data cache line */
+		if (((unsigned int)p & 0x1f) == 0) {
+			ppcDcbz((unsigned long)p);
+		}
+
+		/* write pattern to it and flush */
+		*p = (unsigned int)0xdeadbeef;
+
+		if (((unsigned int)p & 0x1c) == 0x1c) {
+			ppcDcbf((unsigned long)p);
+		}
+	}
 
 	/* 8K */
 	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
@@ -396,13 +501,31 @@ ddr_enable_ecc(unsigned int dram_size)
 	for (i = 1; i < dram_size / 0x800000; i++) {
 		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
 	}
-
-	/*
-	 * Enable errors for ECC.
-	 */
-	ddr->err_disable = 0x00000000;
-	asm("sync;isync");
 #endif
-}
 
+	t_end = get_tbms();
+	icache_disable();
+
+	debug("\nREADY!!\n");
+	debug("ddr init duration: %ld ms\n", t_end - t_start);
+
+	/* Clear All ECC Errors */
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
+		ddr->err_detect |= ECC_ERROR_DETECT_MME;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
+		ddr->err_detect |= ECC_ERROR_DETECT_MBE;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
+		ddr->err_detect |= ECC_ERROR_DETECT_SBE;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
+		ddr->err_detect |= ECC_ERROR_DETECT_MSE;
+
+	/* Disable ECC-Interrupts */
+	ddr->err_int_en &= ECC_ERR_INT_DISABLE;
+
+	/* Enable errors for ECC */
+	ddr->err_disable &= ECC_ERROR_ENABLE;
+
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("isync");
+}
 #endif	/* CONFIG_DDR_ECC */