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authorroy zang <tie-fei.zang@freescale.com>2007-01-04 11:10:05 +0800
committerZang Tiefei <roy@bus.ap.freescale.net>2007-01-04 11:10:05 +0800
commita41969e09b9d886091a804c2ba5f1ab84b084dd3 (patch)
tree96d4b03713537e6c0a696e4770c23f9d39792666 /cpu/mpc8260/pci.c
parentd3bb5ec198edad4869ac5276a5899881b7bf5433 (diff)
parent92eb729bad876725aeea908d2addba0800620840 (diff)
downloadolio-uboot-2014.01-a41969e09b9d886091a804c2ba5f1ab84b084dd3.tar.xz
olio-uboot-2014.01-a41969e09b9d886091a804c2ba5f1ab84b084dd3.zip
Merge branch 'master' into hpc2
Diffstat (limited to 'cpu/mpc8260/pci.c')
-rw-r--r--cpu/mpc8260/pci.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b14fc159b..1edd6fb8d 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -274,7 +274,23 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_CS10PC00
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
-
+#elif defined(CONFIG_TQM8272)
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
+ ~SIUMCR_LBPC11) |
+ SIUMCR_LBPC01 |
+ SIUMCR_CS10PC01 |
+ SIUMCR_APPC10;
+#else
+#if 0
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
+ SIUMCR_APPC10);
+#else
+ immap->im_siu_conf.sc_siumcr = 0x88000000;
+#endif
+#endif
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -288,6 +304,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#endif
+printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits