diff options
| author | wdenk <wdenk> | 2004-06-06 23:13:55 +0000 | 
|---|---|---|
| committer | wdenk <wdenk> | 2004-06-06 23:13:55 +0000 | 
| commit | a56bd92289298bde16306bcc754277db45315d2f (patch) | |
| tree | 191b3ffdc97a005ddc973f7de85ef3b1d3768fd8 /common/miiphyutil.c | |
| parent | 5ca2679933142f7bf2996590b2e318c298664748 (diff) | |
| download | olio-uboot-2014.01-a56bd92289298bde16306bcc754277db45315d2f.tar.xz olio-uboot-2014.01-a56bd92289298bde16306bcc754277db45315d2f.zip | |
* Patch by Dave Peverley, 30 Apr 2004:
  Add support for OMAP730 Perseus2 Development board
* Patch by Alan J. Luse, 29 Apr 2004:
  Fix flash chip-select (OR0) option register setting on FADS boards.
* Patch by Alan J. Luse, 29 Apr 2004:
  Report MII network speed and duplex setting properly when
  auto-negotiate is not enabled.
* Patch by Jarrett Redd, 29 Apr 2004:
  Fix hang on reset on Ocotea board due to flash in wrong mode.
Diffstat (limited to 'common/miiphyutil.c')
| -rw-r--r-- | common/miiphyutil.c | 42 | 
1 files changed, 37 insertions, 5 deletions
| diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 721d109a1..2b0dcf4f2 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -147,15 +147,31 @@ int miiphy_speed (unsigned char addr)  	}  #endif /* CONFIG_PHY_GIGE */ -	if (miiphy_read (addr, PHY_ANLPAR, ®)) { -		puts ("PHY speed1 read failed, assuming 10bT\n"); +	/* Check Basic Management Control Register first. */ +	if (miiphy_read (addr, PHY_BMCR, ®)) { +		puts ("PHY speed read failed, assuming 10bT\n");  		return (_10BASET);  	} -	if ((reg & PHY_ANLPAR_100) != 0) { +	/* Check if auto-negotiation is on. */ +	if ((reg & PHY_BMCR_AUTON) != 0) { +		/* Get auto-negotiation results. */ +		if (miiphy_read (addr, PHY_ANLPAR, ®)) { +			puts ("PHY AN speed read failed, assuming 10bT\n"); +			return (_10BASET); +		} +		if ((reg & PHY_ANLPAR_100) != 0) { +			return (_100BASET); +		} else { +			return (_10BASET); +		} +	} +	/* Get speed from basic control settings. */ +	else if (reg & PHY_BMCR_100MB) {  		return (_100BASET);  	} else {  		return (_10BASET);  	} +  } @@ -182,16 +198,32 @@ int miiphy_duplex (unsigned char addr)  	}  #endif /* CONFIG_PHY_GIGE */ -	if (miiphy_read (addr, PHY_ANLPAR, ®)) { +	/* Check Basic Management Control Register first. */ +	if (miiphy_read (addr, PHY_BMCR, ®)) {  		puts ("PHY duplex read failed, assuming half duplex\n");  		return (HALF);  	} +	/* Check if auto-negotiation is on. */ +	if ((reg & PHY_BMCR_AUTON) != 0) { +		/* Get auto-negotiation results. */ +		if (miiphy_read (addr, PHY_ANLPAR, ®)) { +			puts ("PHY AN duplex read failed, assuming half duplex\n"); +			return (HALF); +		} -	if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) { +		if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) { +			return (FULL); +		} else { +			return (HALF); +		} +	} +	/* Get speed from basic control settings. */ +	else if (reg & PHY_BMCR_DPLX) {  		return (FULL);  	} else {  		return (HALF);  	} +  }  #ifdef CFG_FAULT_ECHO_LINK_DOWN |