Changes to custom pinmux

3 files changed, 320 insertions, 373 deletions

diff --git a/board/olio/h1/h1.c b/board/olio/h1/h1.c
index defdf01e4..c9350347f 100644
--- a/board/olio/h1/h1.c
+++ b/board/olio/h1/h1.c
@@ -36,7 +36,7 @@ int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_H1;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
@@ -83,14 +83,10 @@ int misc_init_r(void)
 	writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
 	printf("Olio H1\n");
 
-	MUX_BEAGLE_XM();
+	//MUX_BEAGLE_XM();
 
 	dieid_num_r();
 
-#ifdef CONFIG_VIDEO_OMAP3
-	omap3_dss_enable();
-#endif
-
 	return 0;
 }
 
@@ -102,5 +98,5 @@ int misc_init_r(void)
  */
 void set_muxconf_regs(void)
 {
-	MUX_BEAGLE();
+	MUX_EVM();
 }
diff --git a/board/olio/h1/h1.h b/board/olio/h1/h1.h
index ec0c24fb9..9361304a6 100644
--- a/board/olio/h1/h1.h
+++ b/board/olio/h1/h1.h
@@ -25,373 +25,8 @@ const omap3_sysinfo sysinfo = {
  * M0   - Mode 0
  * The commented string gives the final mux configuration for that pin
  */
-#define MUX_BEAGLE() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M4)) /*GPIO_131*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M4)) /*GPIO_132*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M4)) /*GPIO_133*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) /*GPIO_134*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4)) /*GPIO_135*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_136*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_138*/\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M1)) /*UART2_RX*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | DIS | M4)) /*GPIO_144*/\
-	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | DIS | M4)) /*GPIO_145*/\
-	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | DIS | M4)) /*GPIO_146*/\
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M4)) /*GPIO_147*/\
- /*Modem Interface */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),		(IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
-	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M4)) /*GPIO_157*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
-	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
- /* USB EHCI (port 2) */\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#define MUX_BEAGLE_C() \
-	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
-	MUX_VAL(CP(UART2_RX),		(IDIS | PTU | EN  | M4)) /*GPIO_147*/
-
-#define MUX_BEAGLE_XM() \
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | EN  | M4)) /*GPIO_56*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IDIS | PTU | EN  | M4)) /*GPIO_63*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTU | EN  | M4)) /*GPIO_129*/\
-	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
 
+#include "pinmux.h"
 /*
  * Display Configuration
  */
diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h
new file mode 100644
index 000000000..6676f9ee1
--- /dev/null
+++ b/board/olio/h1/pinmux.h
@@ -0,0 +1,316 @@
+#ifndef _PINMUX_H_

+#define _PINMUX_H_

+

+/*

+ * M0 - Mux mode 0

+ * M1 - Mux mode 1

+ * M2 - Mux mode 2

+ * M3 - Mux mode 3

+ * M4 - Mux mode 4

+ * M5 - Mux mode 5

+ * M6 - Mux mode 6

+ * M7 - Mux mode 7

+ * IDIS - Input disabled

+ * IEN - Input enabled

+ * PD - Active-mode pull-down enabled

+ * PU - Active-mode pull-up enabled

+ * PI - Active-mode pull inhibited

+ * SB_LOW - Standby mode configuration: Output low-level

+ * SB_HI - Standby mode configuration: Output high-level

+ * SB_HIZ - Standby mode configuration: Output hi-impedence

+ * SB_PD - Standby mode pull-down enabled

+ * SB_PU - Standby mode pull-up enabled

+ * WKEN - Wakeup input enabled

+ */

+

+#define MUX_EVM() \

+/* Design Status: NO ERRORS */\

+MUX_VAL(CONTROL_PADCONF_GPIO_112, (IEN | PD | M4 )) /* gpio_112 */\

+MUX_VAL(CONTROL_PADCONF_GPIO_113, (IEN | PD | M4 )) /* gpio_113 */\

+MUX_VAL(CONTROL_PADCONF_GPIO_114, (IEN | PD | M4 )) /* gpio_114 */\

+MUX_VAL(CONTROL_PADCONF_GPIO_115, (IEN | PD | M4 )) /* gpio_115 */\

+MUX_VAL(CONTROL_PADCONF_GPIO_126, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPIO_127, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPIO_128, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPIO_129, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D0, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D3, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D4, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_VS, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IEN | PU | M4 )) /* gpio_12 */\

+MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IEN | PU | M4 )) /* gpio_13 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PU | M4 )) /* gpio_14 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PU | M4 )) /* gpio_15 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PU | M4 )) /* gpio_16 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PU | M4 )) /* gpio_17 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PD | M4 )) /* gpio_18 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PD | M4 )) /* gpio_19 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PD | M4 )) /* gpio_20 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PD | M4 )) /* gpio_21 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PD | M4 )) /* gpio_22 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PD | M4 )) /* gpio_23 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IEN | PD | M4 )) /* gpio_24 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IEN | PD | M4 )) /* gpio_25 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PD | M4 )) /* gpio_26 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PD | M4 )) /* gpio_27 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PD | M4 )) /* gpio_28 */\

+MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PD | M4 )) /* gpio_29 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | PI | M0 )) /* gpmc_clk */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PU | M0 )) /* gpmc_d0 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PU | M0 )) /* gpmc_d1 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PU | M0 )) /* gpmc_d2 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PU | M0 )) /* gpmc_d3 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PU | M0 )) /* gpmc_d4 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PU | M0 )) /* gpmc_d5 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PU | M0 )) /* gpmc_d6 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PU | M0 )) /* gpmc_d7 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PU | M0 )) /* gpmc_d8 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PU | M0 )) /* gpmc_d9 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PU | M0 )) /* gpmc_d10 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PU | M0 )) /* gpmc_d11 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PU | M0 )) /* gpmc_d12 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PU | M0 )) /* gpmc_d13 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PU | M0 )) /* gpmc_d14 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PU | M0 )) /* gpmc_d15 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | PI | M0 )) /* gpmc_nadv_ale */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | PI | M0 )) /* gpmc_nbe0_cle */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | PI | M0 )) /* gpmc_ncs0 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IDIS | PI | M0 )) /* gpmc_ncs1 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | PI | M0 )) /* gpmc_noe */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | PI | M0 )) /* gpmc_nwe */\

+MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | PI | M0 )) /* gpmc_nwp */\

+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | M0 )) /* gpmc_wait0 */\

+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IDIS | PU | M0 )) /* i2c1_scl */\

+MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PU | M0 )) /* i2c1_sda */\

+MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IDIS | PU | M0 )) /* i2c2_scl */\

+MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PU | M0 )) /* i2c2_sda */\

+MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PU | M0 )) /* i2c3_scl */\

+MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IEN | PU | M0 )) /* i2c3_sda */\

+MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IDIS | PU | M0 )) /* i2c4_scl */\

+MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PU | M0 )) /* i2c4_sda */\

+MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PU | M0 )) /* jtag_emu0 */\

+MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PU | M0 )) /* jtag_emu1 */\

+MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PD | M0 )) /* jtag_ntrst */\

+MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | PI | M0 )) /* jtag_rtck */\

+MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PD | M0 )) /* jtag_tck */\

+MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PU | M0 )) /* jtag_tdi */\

+MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | PI | M0 )) /* jtag_tdo */\

+MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PU | M0 )) /* jtag_tms_tmsc */\

+MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PD | M0 )) /* mcbsp2_clkx */\

+MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PD | M0 )) /* mcbsp2_dr */\

+MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IDIS | PD | M0 )) /* mcbsp2_dx */\

+MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PD | M0 )) /* mcbsp2_fsx */\

+MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IEN | PD | M0 )) /* mcbsp3_clkx */\

+MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IEN | PD | M0 )) /* mcbsp3_dr */\

+MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PD | M0 )) /* mcbsp3_fsx */\

+MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | PI | M0 )) /* sdrc_a0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | PI | M0 )) /* sdrc_a1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | PI | M0 )) /* sdrc_a2 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | PI | M0 )) /* sdrc_a3 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | PI | M0 )) /* sdrc_a4 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | PI | M0 )) /* sdrc_a5 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | PI | M0 )) /* sdrc_a6 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | PI | M0 )) /* sdrc_a7 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | PI | M0 )) /* sdrc_a8 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | PI | M0 )) /* sdrc_a9 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | PI | M0 )) /* sdrc_a10 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | PI | M0 )) /* sdrc_a11 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | PI | M0 )) /* sdrc_a12 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | PI | M0 )) /* sdrc_a13 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | PI | M0 )) /* sdrc_a14 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | PI | M0 )) /* sdrc_ba0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | PI | M0 )) /* sdrc_ba1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | PI | M7 )) /* safe_mode_out1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | PI | M7 )) /* safe_mode_out1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | PI | M0 )) /* sdrc_clk */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | PI | M0 )) /* sdrc_d0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | PI | M0 )) /* sdrc_d1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | PI | M0 )) /* sdrc_d2 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | PI | M0 )) /* sdrc_d3 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | PI | M0 )) /* sdrc_d4 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | PI | M0 )) /* sdrc_d5 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | PI | M0 )) /* sdrc_d6 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | PI | M0 )) /* sdrc_d7 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | PI | M0 )) /* sdrc_d8 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | PI | M0 )) /* sdrc_d9 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | PI | M0 )) /* sdrc_d10 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | PI | M0 )) /* sdrc_d11 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | PI | M0 )) /* sdrc_d12 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | PI | M0 )) /* sdrc_d13 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | PI | M0 )) /* sdrc_d14 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | PI | M0 )) /* sdrc_d15 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | PI | M0 )) /* sdrc_d16 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | PI | M0 )) /* sdrc_d17 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | PI | M0 )) /* sdrc_d18 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | PI | M0 )) /* sdrc_d19 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | PI | M0 )) /* sdrc_d20 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | PI | M0 )) /* sdrc_d21 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | PI | M0 )) /* sdrc_d22 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | PI | M0 )) /* sdrc_d23 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | PI | M0 )) /* sdrc_d24 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | PI | M0 )) /* sdrc_d25 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | PI | M0 )) /* sdrc_d26 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | PI | M0 )) /* sdrc_d27 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | PI | M0 )) /* sdrc_d28 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | PI | M0 )) /* sdrc_d29 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | PI | M0 )) /* sdrc_d30 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | PI | M0 )) /* sdrc_d31 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | PI | M0 )) /* sdrc_dm0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | PI | M0 )) /* sdrc_dm1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | PI | M0 )) /* sdrc_dm2 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | PI | M0 )) /* sdrc_dm3 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | PI | M0 )) /* sdrc_dqs0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | PI | M0 )) /* sdrc_dqs1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | PI | M0 )) /* sdrc_dqs2 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | PI | M0 )) /* sdrc_dqs3 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | PI | M0 )) /* sdrc_ncas */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | PI | M0 )) /* sdrc_nclk */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | PI | M0 )) /* sdrc_ncs0 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | PI | M0 )) /* sdrc_ncs1 */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | PI | M0 )) /* sdrc_nras */\

+MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | PI | M0 )) /* sdrc_nwe */\

+MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | PI | M0 )) /* sys_32k */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | PI | M0 )) /* sys_boot0 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | PI | M0 )) /* sys_boot1 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | PI | M0 )) /* sys_boot2 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | PI | M0 )) /* sys_boot3 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | PI | M0 )) /* sys_boot4 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | PI | M0 )) /* sys_boot5 */\

+MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | PI | M0 )) /* sys_boot6 */\

+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | PI | M4 )) /* gpio_1 */\

+MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PU | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PU | M0 )) /* sys_nreswarm */\

+MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IEN | PD | M7 )) /* safe_mode */\

+MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PD | M0 )) /* uart1_cts */\

+MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | PD | M0 )) /* uart1_rts */\

+MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PD | M0 )) /* uart1_rx */\

+MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | PD | M0 )) /* uart1_tx */\

+MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PU | M4 )) /* gpio_144 */\

+MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PU | M4 )) /* gpio_145 */\

+MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PU | M4 )) /* gpio_147 */\

+MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PU | M4 )) /* gpio_146 */\

+MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, (IEN | PU | M0 )) /* uart3_cts_rctx */\

+MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | PU | M0 )) /* uart3_rts_sd */\

+MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PU | M0 )) /* uart3_rx_irrx */\

+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */

+#endif