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| author | Wolfgang Denk <wd@denx.de> | 2008-06-11 21:33:16 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-06-11 21:33:16 +0200 |
| commit | 5ea67393b8b554b8165c38912d753a8df043020d (patch) | |
| tree | 080077826cffcfebbaa0a950c663e7d165cf6b7d /board/socrates/tlb.c | |
| parent | 2395db48869e759c4422efa3d3c25161601aa17b (diff) | |
| parent | ba04f7010958e88a8910f2a123fee53fdc72e013 (diff) | |
| download | olio-uboot-2014.01-5ea67393b8b554b8165c38912d753a8df043020d.tar.xz olio-uboot-2014.01-5ea67393b8b554b8165c38912d753a8df043020d.zip | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Conflicts:
include/asm-ppc/fsl_lbc.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/socrates/tlb.c')
| -rw-r--r-- | board/socrates/tlb.c | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index b80caea5e..aea99ada2 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = { /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 2: 256M Non-cacheable, guarded @@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), +#if defined(CFG_FPGA_BASE) /* - * TLB 4: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half + * TLB 4: 1M Non-cacheable, guarded + * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), + 0, 4, BOOKE_PAGESZ_1M, 1), +#endif /* * TLB 6: 64M Non-cacheable, guarded |