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| author | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
| commit | 7f673c99c2d8d1aa21996c5b914f06d784b080ca (patch) | |
| tree | df68108a0bd7326dc6299b96853b769220c55470 /board/siemens/dxr2/board.c | |
| parent | 8401bfa91ef57e331e2a3abdf768d41803bec88e (diff) | |
| parent | 10a147bc665367111920be657409a5d56d3c0590 (diff) | |
| download | olio-uboot-2014.01-7f673c99c2d8d1aa21996c5b914f06d784b080ca.tar.xz olio-uboot-2014.01-7f673c99c2d8d1aa21996c5b914f06d784b080ca.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/siemens/dxr2/board.c')
| -rw-r--r-- | board/siemens/dxr2/board.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 3a5e11dc8..6c316faa8 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = { struct cmd_control dxr2_ddr3_cmd_ctrl_data = { }; + +struct ctrl_ioregs dxr2_ddr3_ioregs = { +}; + /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; @@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = { dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; - config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data, + dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val, + dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val, + + config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data, &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); } |