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| author | Stefan Roese <sr@denx.de> | 2008-08-13 06:47:12 +0200 | 
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-08-13 06:47:12 +0200 | 
| commit | 5a7ddf4e1fb9347f783eb1473c30187d7a22bd81 (patch) | |
| tree | 5e30fc06d7bbd5b382b1a7b89f57cd81a5246f32 /board/prodrive/alpr/nand.c | |
| parent | 9939ffd5fbf1f5aff4d8172531d4fc33797c62c8 (diff) | |
| parent | 8641ff266ae6638da201747c239fd39ba34c4958 (diff) | |
| download | olio-uboot-2014.01-5a7ddf4e1fb9347f783eb1473c30187d7a22bd81.tar.xz olio-uboot-2014.01-5a7ddf4e1fb9347f783eb1473c30187d7a22bd81.zip | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/prodrive/alpr/nand.c')
| -rw-r--r-- | board/prodrive/alpr/nand.c | 57 | 
1 files changed, 18 insertions, 39 deletions
| diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 097e18371..99f5737b8 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -56,43 +56,24 @@ static struct alpr_ndfc_regs *alpr_ndfc = NULL;   *   * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).   */ -static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)  { -	switch (cmd) { -	case NAND_CTL_SETCLE: -		hwctl |= 0x1; -		break; -	case NAND_CTL_CLRCLE: -		hwctl &= ~0x1; -		break; -	case NAND_CTL_SETALE: -		hwctl |= 0x2; -		break; -	case NAND_CTL_CLRALE: -		hwctl &= ~0x2; -		break; -	case NAND_CTL_SETNCE: -		break; -	case NAND_CTL_CLRNCE: -		writeb(0x00, &(alpr_ndfc->term)); -		break; -	} -} - -static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) -{ -	struct nand_chip *nand = mtd->priv; +	struct nand_chip *this = mtd->priv; -	if (hwctl & 0x1) -		/* -		 * IO_ADDR_W used as CMD[i] reg to support multiple NAND -		 * chips. -		 */ -		writeb(byte, nand->IO_ADDR_W); -	else if (hwctl & 0x2) { -		writeb(byte, &(alpr_ndfc->addr_wait)); -	} else -		writeb(byte, &(alpr_ndfc->data)); +	if (ctrl & NAND_CTRL_CHANGE) { +		if ( ctrl & NAND_CLE ) +			hwctl |= 0x1; +		else +			hwctl &= ~0x1; +		if ( ctrl & NAND_ALE ) +			hwctl |= 0x2; +		else +			hwctl &= ~0x2; +		if ( (ctrl & NAND_NCE) != NAND_NCE) +			writeb(0x00, &(alpr_ndfc->term)); +	} +	if (cmd != NAND_CMD_NONE) +		writeb(cmd, this->IO_ADDR_W);  }  static u_char alpr_nand_read_byte(struct mtd_info *mtd) @@ -158,12 +139,10 @@ int board_nand_init(struct nand_chip *nand)  {  	alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; -	nand->eccmode = NAND_ECC_SOFT; +	nand->ecc.mode = NAND_ECC_SOFT;  	/* Reference hardware control function */ -	nand->hwcontrol  = alpr_nand_hwcontrol; -	/* Set command delay time */ -	nand->write_byte = alpr_nand_write_byte; +	nand->cmd_ctrl  = alpr_nand_hwcontrol;  	nand->read_byte  = alpr_nand_read_byte;  	nand->write_buf  = alpr_nand_write_buf;  	nand->read_buf   = alpr_nand_read_buf; |