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| author | mattis fjallstrom <mattis@acm.org> | 2015-09-06 11:09:39 -0700 |
|---|---|---|
| committer | mattis fjallstrom <mattis@acm.org> | 2015-09-06 11:09:39 -0700 |
| commit | ee87ec4d2c955c929a4c27ce8a56f918444cf955 (patch) | |
| tree | c18141755ad893eddd5b504e4cf096ad4e7062b9 /board/olio/h1/pinmux.h | |
| parent | 2c25de1ed5c6f8f6bba3b5ec506f430d8a883a83 (diff) | |
| download | olio-uboot-2014.01-ee87ec4d2c955c929a4c27ce8a56f918444cf955.tar.xz olio-uboot-2014.01-ee87ec4d2c955c929a4c27ce8a56f918444cf955.zip | |
First fastboot commit, MLO built here wont work so be careful.
Change-Id: Ic8d65a92da82896282eee71cf0d0515f64c939bc
Diffstat (limited to 'board/olio/h1/pinmux.h')
| -rw-r--r-- | board/olio/h1/pinmux.h | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h index 23cfede2e..3861c3bad 100644 --- a/board/olio/h1/pinmux.h +++ b/board/olio/h1/pinmux.h @@ -146,15 +146,15 @@ MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 | SB_PU)) /* safe_mode - edit 2014-05-11 */ \
MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PD | M7 | SB_PD)) /* safe_mode - edit 2014-05-11 */ \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\ MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PD | M7 )) /* safe_mode */\
MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IEN | PU | M7 )) /* safe_mode */\
@@ -312,5 +312,18 @@ MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PU | M4 )) /* gpio_146 */\ MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, (IEN | PU | M0 )) /* uart3_cts_rctx */\
MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | PU | M0 )) /* uart3_rts_sd */\
MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PU | M0 )) /* uart3_rx_irrx */\
-MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PI | M0 )) /* hsusb0_clk */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PI | M0)) /* hsusb0_data0 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PI | M0)) /* hsusb0_data1 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PI | M0)) /* hsusb0_data2 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PI | M0)) /* hsusb0_data3 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PI | M0)) /* hsusb0_data4 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PI | M0)) /* hsusb0_data5 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PI | M0)) /* hsusb0_data6 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PI | M0)) /* hsusb0_data7 */\ +MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PI | M0)) /*hsusb0_dir */ \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PI | M0)) /*hsusb0_stp */ \ +MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PI | M0)) /*hsusb0_nxt */ \ +MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IDIS | PI | M4)) /* gpio_17 */ #endif
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