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| author | Andre Schwarz <andre.schwarz@matrix-vision.de> | 2008-07-09 18:30:44 +0200 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2008-07-15 10:12:58 -0600 |
| commit | 5e0de0e216b8fb27634afb11c60a2fa24c23349e (patch) | |
| tree | 9658cd67b59fa936cfc535eb7e093d3d0f97a008 /board/matrix_vision/mvbc_p/mvbc_p.h | |
| parent | 348753d416cd2c9e7ec6520a544c8f33cf02a560 (diff) | |
| download | olio-uboot-2014.01-5e0de0e216b8fb27634afb11c60a2fa24c23349e.tar.xz olio-uboot-2014.01-5e0de0e216b8fb27634afb11c60a2fa24c23349e.zip | |
mpc5xxx: Add MVBC_P board support
The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000) and custom Altera Cyclone-II FPGA on PCI.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'board/matrix_vision/mvbc_p/mvbc_p.h')
| -rw-r--r-- | board/matrix_vision/mvbc_p/mvbc_p.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h new file mode 100644 index 000000000..33307981e --- /dev/null +++ b/board/matrix_vision/mvbc_p/mvbc_p.h @@ -0,0 +1,43 @@ +#ifndef __MVBC_H__ +#define __MVBC_H__ + +#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0 +#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1 +#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2 +#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3 +#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4 + +#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 +#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 +#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 +#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 +#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 + +#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 +#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 +#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 +#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 +#define FACT_RST MPC5XXX_GPIO_WKUP_6 +#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 + +#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ + FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) +#define SIMPLE_DVO (FPGA_CONFIG) +#define SIMPLE_ODE (FPGA_CONFIG) +#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ + FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ + WD_WDI | COP_PRESENT) + +#define SINT_ODE 0 +#define SINT_DDR 0 +#define SINT_DVO 0 +#define SINT_INTEN 0 +#define SINT_ITYPE 0 +#define SINT_GPIOEN (FPGA_STATUS) + +#define WKUP_ODE (MAN_RST) +#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS) +#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS) +#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY) + +#endif |