diff options
| author | Peter Barada <peter.barada@logicpd.com> | 2012-02-07 08:15:51 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 10:11:32 +0100 |
| commit | a8baf8e25fe25841fef6fc05628a6d04021f25b4 (patch) | |
| tree | b4f0577f3b17826d4a7667f14ffb310869025f77 /board/logicpd/omap3som/omap3logic.c | |
| parent | c8ff6a9ed9e3646d7281539ee3f8699848f5ab6f (diff) | |
| download | olio-uboot-2014.01-a8baf8e25fe25841fef6fc05628a6d04021f25b4.tar.xz olio-uboot-2014.01-a8baf8e25fe25841fef6fc05628a6d04021f25b4.zip | |
omap3logic: Add missing GPMC pinmux for LAN92xx access
The initial checkin dropped pinmux setup for GPMC pins A6-A10, D0-D7 and
NCS1/2 necessary to access LAN92xx on Logic OMAP35x/DM37x modules.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Diffstat (limited to 'board/logicpd/omap3som/omap3logic.c')
| -rw-r--r-- | board/logicpd/omap3som/omap3logic.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 4f5fa8d25..bc7ec68f1 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -200,6 +200,19 @@ void set_muxconf_regs(void) MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); @@ -209,6 +222,8 @@ void set_muxconf_regs(void) MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0)); MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4)); MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/ |