diff options
| author | Tom Rini <trini@ti.com> | 2014-03-07 20:54:22 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-03-07 20:54:22 -0500 |
| commit | 247161b8160fc699b0a517f081220bb50bc502a8 (patch) | |
| tree | 24390c70879de9500b51d8ba0b8f2744bf8fa481 /board/freescale/t104xrdb/ddr.c | |
| parent | d57d60cf24e46aab144511d110dee7d068da6e66 (diff) | |
| parent | 96ac18c9ccc77c7f57dff5651b34a3cc914c8abd (diff) | |
| download | olio-uboot-2014.01-247161b8160fc699b0a517f081220bb50bc502a8.tar.xz olio-uboot-2014.01-247161b8160fc699b0a517f081220bb50bc502a8.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t104xrdb/ddr.c')
| -rw-r--r-- | board/freescale/t104xrdb/ddr.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 9009afa3a..57d0f9cfd 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -46,7 +46,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp = udimms[0]; - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr + /* Get clk_adjust according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -54,14 +54,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -74,13 +70,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -112,8 +105,8 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); } phys_size_t initdram(int board_type) |