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| author | Xie Xiaobo <X.Xie@freescale.com> | 2013-06-24 15:01:30 +0800 | 
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:25 -0700 | 
| commit | 49f5befafd0f71e3ba033081e80fa4965d682ebc (patch) | |
| tree | 4d68958c31044c662cd63fc67c4846c6995ac133 /board/freescale/p1_twr/tlb.c | |
| parent | d05bfd0586ccebe96e31976459c8ef45ec65e109 (diff) | |
| download | olio-uboot-2014.01-49f5befafd0f71e3ba033081e80fa4965d682ebc.tar.xz olio-uboot-2014.01-49f5befafd0f71e3ba033081e80fa4965d682ebc.zip | |
powerpc/85xx: Add TWR-P10xx board support
TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot
Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY
UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor
USB: Two USB2.0 Type A ports
I2C:
   AT24C01B 1K Board EEPROM (8 bit address)
QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232
PCIE:
   One mini-PCIE slot
Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/p1_twr/tlb.c')
| -rw-r--r-- | board/freescale/p1_twr/tlb.c | 92 | 
1 files changed, 92 insertions, 0 deletions
| diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c new file mode 100644 index 000000000..68e109c95 --- /dev/null +++ b/board/freescale/p1_twr/tlb.c @@ -0,0 +1,92 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { +	/* TLB 0 - for temp stack in cache */ +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, +			CONFIG_SYS_INIT_RAM_ADDR_PHYS, +			MAS3_SX|MAS3_SW|MAS3_SR, 0, +			0, 0, BOOKE_PAGESZ_4K, 0), +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, +			MAS3_SX|MAS3_SW|MAS3_SR, 0, +			0, 0, BOOKE_PAGESZ_4K, 0), +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, +			MAS3_SX|MAS3_SW|MAS3_SR, 0, +			0, 0, BOOKE_PAGESZ_4K, 0), +	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , +			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, +			MAS3_SX|MAS3_SW|MAS3_SR, 0, +			0, 0, BOOKE_PAGESZ_4K, 0), + +	/* TLB 1 */ +	/* *I*** - Covers boot page */ +	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, +			0, 0, BOOKE_PAGESZ_4K, 1), + +	/* *I*G* - CCSRBAR */ +	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, +			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, +			0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_SPL_BUILD +	/* W**G* - Flash, localbus */ +	/* This will be changed to *I*G* after relocation to RAM. */ +	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, +			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, +			0, 2, BOOKE_PAGESZ_64M, 1), + +	/* W**G* - Flash, localbus */ +	/* This will be changed to *I*G* after relocation to RAM. */ +	SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, +			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, +			0, 5, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCI +	/* *I*G* - PCI memory 1.5G */ +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, +			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, +			0, 3, BOOKE_PAGESZ_1G, 1), + +	/* *I*G* - PCI I/O effective: 192K  */ +	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, +			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, +			0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#endif + +#ifdef CONFIG_SYS_RAMBOOT +	/* *I*G - eSDHC boot */ +	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, +			MAS3_SX|MAS3_SW|MAS3_SR, 0, +			0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |