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| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /board/fads/fads.c | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
| download | olio-uboot-2014.01-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.xz olio-uboot-2014.01-8ed44d91c8122d00368523b0b746691c895d3b3c.zip | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/fads/fads.c')
| -rw-r--r-- | board/fads/fads.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/fads/fads.c b/board/fads/fads.c index 278fa2ab2..9f7faaf47 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -449,19 +449,19 @@ static int _initsdram(uint base, uint noMbytes) /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */ + memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ + /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ udelay(200); /* Run 8 refresh cycles */ - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/ + memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ udelay(200); - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */ + memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ + memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ udelay(200); |