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| author | Graeme Russ <graeme.russ@gmail.com> | 2010-04-24 00:05:56 +1000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-05-06 00:19:19 +0200 |
| commit | 4a4c31ae08d4dcabe348013e135de28b01c29bf0 (patch) | |
| tree | 57df1cc0baef41b91b157c66a0b3e61cab088103 /board/eNET/eNET.c | |
| parent | 8fd805632f95e5e834f312a51aa969bf1d99c41b (diff) | |
| download | olio-uboot-2014.01-4a4c31ae08d4dcabe348013e135de28b01c29bf0.tar.xz olio-uboot-2014.01-4a4c31ae08d4dcabe348013e135de28b01c29bf0.zip | |
eNET: Add PC/AT compatibility setup function
The eNET uses the sc520 software timers rather than the PC/AT clones
Set all interrupts and timers up to be PC/AT compatible
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Diffstat (limited to 'board/eNET/eNET.c')
| -rw-r--r-- | board/eNET/eNET.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 62f99ce94..ad71f7e5d 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -180,3 +180,41 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +void setup_pcat_compatibility() +{ + /* disable global interrupt mode */ + writeb(0x40, &sc520_mmcr->picicr); + + /* set all irqs to edge */ + writeb(0x00, &sc520_mmcr->pic_mode[0]); + writeb(0x00, &sc520_mmcr->pic_mode[1]); + writeb(0x00, &sc520_mmcr->pic_mode[2]); + + /* + * active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins + */ + writew(0x0000,&sc520_mmcr->intpinpol); + + /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */ + writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]); + writeb(SC520_IRQ8, &sc520_mmcr->rtcmap); + writeb(SC520_IRQ13, &sc520_mmcr->ferrmap); + + /* Disable all other interrupt sources */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */ + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap); + writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap); +} |