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| author | Matthew McClintock <msm@freescale.com> | 2012-08-13 08:10:37 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 10:24:16 -0500 |
| commit | 9c6b47d53ed329b31c5f26e9ec710f67559c07f0 (patch) | |
| tree | e249bf392017d29d3a90389685ac2f972c5fc4a9 /arch/powerpc/include/asm/fsl_ddr_sdram.h | |
| parent | be7bebeac24f33bd7eef2f5047579c1a680d8df1 (diff) | |
| download | olio-uboot-2014.01-9c6b47d53ed329b31c5f26e9ec710f67559c07f0.tar.xz olio-uboot-2014.01-9c6b47d53ed329b31c5f26e9ec710f67559c07f0.zip | |
p1014rdb: set ddr bus width properly depending on SVR
Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_ddr_sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 93639ba85..157ae2463 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -88,6 +88,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 |