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| author | Wolfgang Denk <wd@denx.de> | 2010-09-28 23:30:47 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-09-28 23:30:47 +0200 |
| commit | 2e6e1772c0e34871769be4aef79748fe3e47d953 (patch) | |
| tree | 00e4e19d7bccd2a1cd5753854ff4c2b8a26bebb0 /arch/powerpc/cpu/ppc4xx/cpu_init.c | |
| parent | 1e4e5ef0469050f014aee1204dae8a9ab6053e49 (diff) | |
| parent | 3df61957938586c512c17e72d83551d190400981 (diff) | |
| download | olio-uboot-2014.01-2e6e1772c0e34871769be4aef79748fe3e47d953.tar.xz olio-uboot-2014.01-2e6e1772c0e34871769be4aef79748fe3e47d953.zip | |
Merge branch 'next' of /home/wd/git/u-boot/next
Conflicts:
include/ppc4xx.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/cpu_init.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index b31bd0bcc..d54b30e26 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -23,10 +23,10 @@ #include <common.h> #include <watchdog.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> #include <asm/processor.h> -#include <asm/gpio.h> -#include <ppc4xx.h> +#include <asm/ppc4xx-gpio.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; @@ -266,7 +266,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -397,10 +397,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | - PLB0_ACR_RDP_4DEEP); - mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | - PLB1_ACR_RDP_4DEEP); + mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); + mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } |