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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
| commit | a19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch) | |
| tree | 1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /arch/powerpc/cpu/mpc8xxx/ddr/main.c | |
| parent | 60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff) | |
| parent | a71d45d706a5b51c348160163b6c159632273fed (diff) | |
| download | olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.xz olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/main.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/main.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 5311a262a..7a8636de1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) { return step_string_tbl[s]; } -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, +static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, unsigned int dbw_cap_adj[]) { int i, j; @@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, return total_mem; } +/* Use weak function to allow board file to override the address assignment */ +__attribute__((weak, alias("__step_assign_addresses"))) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]); + unsigned long long fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only) @@ -541,14 +546,17 @@ phys_size_t fsl_ddr_sdram(void) total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* setup 3-way interleaving before enabling DDRC */ - switch (info.memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode); - break; - default: - break; + if (info.memctl_opts[0].memctl_interleaving) { + switch (info.memctl_opts[0].memctl_interleaving_mode) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + fsl_ddr_set_intl3r( + info.memctl_opts[0].memctl_interleaving_mode); + break; + default: + break; + } } /* Program configuration registers. */ |