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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-09-25 10:41:19 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:16 -0700 |
| commit | 0dd38a35f462b3ba28a49cda2dc80ef57eb52acd (patch) | |
| tree | bfb78890aed1b2b08a3ecbeaaefcc03e79e6b9c2 /arch/powerpc/cpu/mpc8xxx/ddr/main.c | |
| parent | 262737f05aa94b29d24f21d7eae89756c242df8e (diff) | |
| download | olio-uboot-2014.01-0dd38a35f462b3ba28a49cda2dc80ef57eb52acd.tar.xz olio-uboot-2014.01-0dd38a35f462b3ba28a49cda2dc80ef57eb52acd.zip | |
powerpc: Fix CamelCase warnings in DDR related code
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl
Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/main.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 842bf1989..b9ae9509b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -457,7 +457,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * which is currently STEP_ASSIGN_ADDRESSES. */ populate_memctl_options( - timing_params[i].all_DIMMs_registered, + timing_params[i].all_dimms_registered, &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); /* @@ -466,7 +466,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * using fixed parameters, this function should be * be called from board init file. */ - if (timing_params[i].all_DIMMs_registered) + if (timing_params[i].all_dimms_registered) assert_reset = 1; } if (assert_reset) { @@ -589,7 +589,7 @@ phys_size_t fsl_ddr_sdram(void) */ deassert_reset = board_need_mem_reset(); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.common_timing_params[i].all_DIMMs_registered) + if (info.common_timing_params[i].all_dimms_registered) deassert_reset = 1; } for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |