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| author | Becky Bruce <beckyb@kernel.crashing.org> | 2010-06-17 11:37:21 -0500 | 
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-07-16 10:55:09 -0500 | 
| commit | 4e63df300f05df2eb3ee87deed043a718ffc6a4e (patch) | |
| tree | ef7238884c0159a6ba6b0f2888ec25d1ea6a5183 /arch/powerpc/cpu/mpc85xx/tlb.c | |
| parent | f51cdaf19141151ce2b40d562a468605340f2315 (diff) | |
| download | olio-uboot-2014.01-4e63df300f05df2eb3ee87deed043a718ffc6a4e.tar.xz olio-uboot-2014.01-4e63df300f05df2eb3ee87deed043a718ffc6a4e.zip | |
mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code.  Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/tlb.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/tlb.c | 50 | 
1 files changed, 24 insertions, 26 deletions
| diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index b3037acea..eebb6ae04 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,6 +55,24 @@ void init_tlbs(void)  	return ;  } +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, +		       phys_addr_t *rpn) +{ +	u32 _mas1; + +	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); +	asm volatile("tlbre;isync"); +	_mas1 = mfspr(MAS1); + +	*valid = (_mas1 & MAS1_VALID); +	*tsize = (_mas1 >> 8) & 0xf; +	*epn = mfspr(MAS2) & MAS2_EPN; +	*rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS +	*rpn |= ((u64)mfspr(MAS7)) << 32; +#endif +} +  #ifndef CONFIG_NAND_SPL  static inline void use_tlb_cam(u8 idx)  { @@ -82,15 +100,9 @@ void init_used_tlb_cams(void)  	/* walk all the entries */  	for (i = 0; i < num_cam; i++) { -		u32 _mas1; -  		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); -  		asm volatile("tlbre;isync"); -		_mas1 = mfspr(MAS1); - -		/* if the entry isn't valid skip it */ -		if ((_mas1 & MAS1_VALID)) +		if (mfspr(MAS1) & MAS1_VALID)  			use_tlb_cam(i);  	}  } @@ -134,7 +146,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,  #ifdef CONFIG_ADDR_MAP  	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) -		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); +		addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);  #endif  } @@ -201,26 +213,12 @@ void init_addr_map(void)  	/* walk all the entries */  	for (i = 0; i < num_cam; i++) {  		unsigned long epn; -		u32 tsize, _mas1; +		u32 tsize, valid;  		phys_addr_t rpn; -		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - -		asm volatile("tlbre;isync"); -		_mas1 = mfspr(MAS1); - -		/* if the entry isn't valid skip it */ -		if (!(_mas1 & MAS1_VALID)) -			continue; - -		tsize = (_mas1 >> 8) & 0xf; -		epn = mfspr(MAS2) & MAS2_EPN; -		rpn = mfspr(MAS3) & MAS3_RPN; -#ifdef CONFIG_ENABLE_36BIT_PHYS -		rpn |= ((phys_addr_t)mfspr(MAS7)) << 32; -#endif - -		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i); +		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); +		if (valid & MAS1_VALID) +			addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);  	}  	return ; |