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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
| commit | a19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch) | |
| tree | 1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /arch/powerpc/cpu/mpc85xx/speed.c | |
| parent | 60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff) | |
| parent | a71d45d706a5b51c348160163b6c159632273fed (diff) | |
| download | olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.xz olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/speed.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 297f2ed47..a4d6e9cc7 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -112,30 +112,32 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* * Each cluster has up to 4 cores, sharing the same PLL selection. - * The cluster assignment is fixed per SoC. There is no way identify the - * assignment so far, presuming the "first configuration" which is to - * fill the lower cluster group first before moving up to next group. - * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1 - * and core 4~7 on cluster 2 - * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3 - * and core 12~15 on cluster 4 if existing + * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are + * cluster group A, feeding cores on cluster 1 and cluster 2. + * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 + * and cluster 4 if existing. */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27) + int cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; if (cplx_pll > 3) printf("Unsupported architecture configuration" " in function %s\n", __func__); - cplx_pll += (cpu / 8) * 3; - + cplx_pll += (cluster / 2) * 3; sysInfo->freqProcessor[cpu] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; } +#ifdef CONFIG_PPC_B4860 +#define FM1_CLK_SEL 0xe0000000 +#define FM1_CLK_SHIFT 29 +#else #define PME_CLK_SEL 0xe0000000 #define PME_CLK_SHIFT 29 #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME @@ -185,6 +187,9 @@ void get_sys_info (sys_info_t * sysInfo) case 4: sysInfo->freqFMan[0] = freqCC_PLL[3] / 4; break; + case 5: + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; + break; case 6: sysInfo->freqFMan[0] = freqCC_PLL[4] / 2; break; @@ -232,7 +237,8 @@ void get_sys_info (sys_info_t * sysInfo) #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; sysInfo->freqProcessor[cpu] = @@ -285,6 +291,10 @@ void get_sys_info (sys_info_t * sysInfo) #endif #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + sysInfo->freqQMAN = sysInfo->freqSystemBus / 2; +#endif + #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ |