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| author | Alison Wang <b18965@freescale.com> | 2012-03-26 21:49:05 +0000 |
|---|---|---|
| committer | jason <jason@jason-ThinkPad-T61.(none)> | 2012-09-20 20:39:27 +0800 |
| commit | aa0d99fc285a0b4ca71245c0c3ba8c00f8b51983 (patch) | |
| tree | b5d08e72a224b9e7b9768c4f822bb6366f034da7 /arch/m68k/cpu/mcf532x/interrupts.c | |
| parent | 32dbaafa5a1fda97dbf99e6627309e7570dc14ca (diff) | |
| download | olio-uboot-2014.01-aa0d99fc285a0b4ca71245c0c3ba8c00f8b51983.tar.xz olio-uboot-2014.01-aa0d99fc285a0b4ca71245c0c3ba8c00f8b51983.zip | |
ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x
Signed-off-by: Alison Wang <b18965@freescale.com>
Diffstat (limited to 'arch/m68k/cpu/mcf532x/interrupts.c')
| -rw-r--r-- | arch/m68k/cpu/mcf532x/interrupts.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index d6c820545..d1ea2ff5a 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -41,9 +42,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif |