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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
| commit | a19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch) | |
| tree | 1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /arch/blackfin/cpu/cpu.c | |
| parent | 60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff) | |
| parent | a71d45d706a5b51c348160163b6c159632273fed (diff) | |
| download | olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.xz olio-uboot-2014.01-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
Diffstat (limited to 'arch/blackfin/cpu/cpu.c')
| -rw-r--r-- | arch/blackfin/cpu/cpu.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 0be2e2b83..218f57ed3 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -16,13 +16,39 @@ #include <asm/mach-common/bits/core.h> #include <asm/mach-common/bits/ebiu.h> #include <asm/mach-common/bits/trace.h> +#include <asm/serial.h> #include "cpu.h" -#include "serial.h" #include "initcode.h" ulong bfin_poweron_retx; +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) +void bfin_core1_start(void) +{ +#ifdef BF561_FAMILY + /* Enable core 1 */ + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); +#else + /* Enable core 1 */ + bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START); + bfin_write32(RCU0_CRCTL, 0); + + bfin_write32(RCU0_CRCTL, 0x2); + + /* Check if core 1 starts */ + while (!(bfin_read32(RCU0_CRSTAT) & 0x2)) + continue; + + bfin_write32(RCU0_CRCTL, 0); + + /* flag to notify cces core 1 application */ + bfin_write32(SDU0_MSG_SET, (1 << 19)); +#endif +} +#endif + +__attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 @@ -72,6 +98,10 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) # endif #endif +#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START) + bfin_core1_start(); +#endif + serial_early_puts("Board init flash\n"); board_init_f(bootflag); } |