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| author | Heiko Schocher <hs@denx.de> | 2010-09-17 13:10:30 +0200 | 
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-09-19 19:29:51 +0200 | 
| commit | c3330e9d6a11b6ead4a2346001338ce884b5832b (patch) | |
| tree | f4fddc3272964e0cc047308533e6c2f642ee5870 /arch/arm/lib/cache.c | |
| parent | 880eff5cfb9df6f0855f4e48affd349ca64692e9 (diff) | |
| download | olio-uboot-2014.01-c3330e9d6a11b6ead4a2346001338ce884b5832b.tar.xz olio-uboot-2014.01-c3330e9d6a11b6ead4a2346001338ce884b5832b.zip | |
ARM (ARM926ejs): add data cache support, tested on magnesium and tx25 board
Enable "cache" command on tx25 and magnesium board and test performance.
    Test 1: Loading 127 MB of data from NAND flash into RAM:
    Instr. Cache        off     on      on
      Data Cache        off     off     on
    --------------------------------------------------
    magnesium           32,6s   22,5s   30s     = x 1,09
    tx25 (29MB only)    9,69s   5,05s   8,16s   = x 1,19
    Test 2: uncompressing a gzipped image from RAM to RAM
            (size compressed: 6.5 MiB, uncompressed: 35 MiB):
    Instr. Cache        off     on      on
      Data Cache        off     off     on
    --------------------------------------------------
    magnesium           4,25s   2,08s   1,72s   = x 2,47
    tx25                4,82s   2,04s   1,84s   = x 2,62
Portions of this work were supported by funding from
the CE Linux Forum.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Alessandro Rubini <rubini@gnudd.com>
Diffstat (limited to 'arch/arm/lib/cache.c')
| -rw-r--r-- | arch/arm/lib/cache.c | 6 | 
1 files changed, 6 insertions, 0 deletions
| diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 61ee9d3b1..b36fd2440 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -32,5 +32,11 @@ void  flush_cache (unsigned long dummy1, unsigned long dummy2)  	arm1136_cache_flush();  #endif +#ifdef CONFIG_ARM926EJS +	/* test and clean, page 2-23 of arm926ejs manual */ +	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); +	/* disable write buffer as well (page 2-22) */ +	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif  	return;  } |