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| author | Tom Rini <trini@ti.com> | 2013-03-18 12:31:00 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-18 14:37:18 -0400 |
| commit | 0ce033d2582129243aca10d3072a221386bbba44 (patch) | |
| tree | 6e50a3f4eed22007549dc740d0fa647a6c8cec5b /arch/arm/include/asm/emif.h | |
| parent | b5bec88434adb52413f1bc33fa63d7642cb8fd35 (diff) | |
| parent | b27673ccbd3d5435319b5c09c3e7061f559f925d (diff) | |
| download | olio-uboot-2014.01-0ce033d2582129243aca10d3072a221386bbba44.tar.xz olio-uboot-2014.01-0ce033d2582129243aca10d3072a221386bbba44.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end. We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.
Conflicts:
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot.lds
arch/arm/lib/Makefile
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/dvlhost/u-boot.lds
board/freescale/mx31ads/u-boot.lds
doc/README.scrapyard
include/configs/tegra-common.h
Build tested for all of ARM and run-time tested on am335x_evm.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/emif.h')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index ed251ec8e..c5d1e6c83 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -519,6 +519,7 @@ #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 /* DMM */ #define DMM_BASE 0x4E000040 @@ -696,11 +697,9 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_1; u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; + u8 is_ma_present; }; -extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; -extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - #define CS0 0 #define CS1 1 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ @@ -1027,6 +1026,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; @@ -1129,6 +1133,14 @@ struct emif_regs { u32 emif_rd_wr_exec_thresh; }; +struct lpddr2_mr_regs { + s8 mr1; + s8 mr2; + s8 mr3; + s8 mr10; + s8 mr16; +}; + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) @@ -1148,6 +1160,7 @@ void emif_get_device_timings(u32 emif_nr, #endif void do_ext_phy_settings(u32 base, const struct emif_regs *regs); +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; @@ -1156,4 +1169,5 @@ extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); +u32 emif_sdram_type(void); #endif |