Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  tegra2: Optimize out-of-tree build for Ventana.
  tegra: Move boards over to use arch-level board UART function
  tegra: Add support for UART init in cpu board.c
  tegra: Add a function mux feature
  tegra: add clock_ll_start_uart() to enable UART prior to reloc
  tegra: Move clock_early_init() to arch_cpu_init()
  tegra: Move cpu_init_cp15() to arch_cpu_init()
  arm: Tegra: Fix Harmony and Ventana builds in u-boot-tegra/master
  tegra: Fix build error in plutux, medcom
  tegra2: Add Avionic Design Medcom support.
  tegra2: Add Avionic Design Plutux support.
  tegra2: Add common Avionic Design Tamonten support.
  tegra2: Move tegra2_mmc_init() prototype to public header.
  tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000.
  tegra2: Always build with USE_PRIVATE_LIBGCC=yes.
  tegra2: Plumb in SPI/UART switch code
  tegra2: spi: Support SPI / UART switch
  tegra2: Implement SPI / UART GPIO switch
  tegra2: Enable SPI environment on Seaboard
  tegra2: config: Enable SPI flash on Seaboard
  tegra2: spi: Add SPI driver for Tegra2 SOC
  tegra2: Add UARTB support
  tegra2: Tidy UART selection
  arm, davinci: Fix build warnings for cam_enc_4xx
  Devkit8000: Switch over to enable_gpmc_cs_config
  arm, davinci: Add support for generating AIS images to the Makefile
  mkimage: Fix variable length header support
  arm, da850evm: Add an SPL for SPI boot
  arm, davinci: Add SPL support for DA850 SoCs
  sf: Add spi_boot() to allow booting from SPI flash in an SPL
  spl: display_options.o is required for SPI flash support in SPL
  ARM: omap3: add support to Technexion twister board
  ARM: omap3: added common configuration for Technexion TAM3517
  vision2: Fix checkpatch warning

1 files changed, 76 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
new file mode 100644
index 000000000..ceec4287a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
@@ -0,0 +1,76 @@
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_SPI_H_
+#define _TEGRA2_SPI_H_
+
+#include <asm/types.h>
+
+struct spi_tegra {
+	u32 command;	/* SPI_COMMAND_0 register  */
+	u32 status;	/* SPI_STATUS_0 register */
+	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
+	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
+	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
+	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
+	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
+};
+
+#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
+#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT	18
+#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL			(1 << 16)
+#define SPI_CMD_TXEN			(1 << 15)
+#define SPI_CMD_RXEN			(1 << 14)
+#define SPI_CMD_CS_VAL			(1 << 13)
+#define SPI_CMD_CS_SOFT			(1 << 12)
+#define SPI_CMD_CS_DELAY		(1 << 9)
+#define SPI_CMD_CS3_EN			(1 << 8)
+#define SPI_CMD_CS2_EN			(1 << 7)
+#define SPI_CMD_CS1_EN			(1 << 6)
+#define SPI_CMD_CS0_EN			(1 << 5)
+#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+
+#define SPI_STAT_BSY			(1 << 31)
+#define SPI_STAT_RDY			(1 << 30)
+#define SPI_STAT_RXF_FLUSH		(1 << 29)
+#define SPI_STAT_TXF_FLUSH		(1 << 28)
+#define SPI_STAT_RXF_UNR		(1 << 27)
+#define SPI_STAT_TXF_OVF		(1 << 26)
+#define SPI_STAT_RXF_EMPTY		(1 << 25)
+#define SPI_STAT_RXF_FULL		(1 << 24)
+#define SPI_STAT_TXF_EMPTY		(1 << 23)
+#define SPI_STAT_TXF_FULL		(1 << 22)
+#define SPI_STAT_SEL_TXRX_N		(1 << 16)
+#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA2_SPI_MAX_FREQ	52000000
+
+
+#endif	/* _TEGRA2_SPI_H_ */