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| author | Tom Warren <twarren@nvidia.com> | 2013-03-25 16:22:26 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 11:01:38 -0700 |
| commit | d0edce4fa394325a0ccfd38a5d668fb5ee1af34d (patch) | |
| tree | 5a7ea0c182d9b2c33699fcfff230f83ba7b4ff84 /arch/arm/cpu/tegra-common/ap.c | |
| parent | 85434f9d7123c283b2233614178e7cfc968d329b (diff) | |
| download | olio-uboot-2014.01-d0edce4fa394325a0ccfd38a5d668fb5ee1af34d.tar.xz olio-uboot-2014.01-d0edce4fa394325a0ccfd38a5d668fb5ee1af34d.zip | |
Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.
Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common/ap.c')
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 3f30805ed..a739fe2b5 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -139,11 +139,6 @@ void s_init(void) enable_scu(); - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have SoC's L2 disabled too? */ + /* init the cache */ + config_cache(); } |