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| author | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
| commit | 3e4d27b06d7484040355e22eec2cbce7335d6dab (patch) | |
| tree | 9672a2bb2e4ce0edc0ab776ddf0e2ca8e39a5f62 /arch/arm/cpu/armv7/omap3/board.c | |
| parent | bad05afe083eec0467220de21683443292c5012e (diff) | |
| parent | 59852d03867108217fe88e3bfc3e1e9cedfe63c5 (diff) | |
| download | olio-uboot-2014.01-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.xz olio-uboot-2014.01-3e4d27b06d7484040355e22eec2cbce7335d6dab.zip | |
Merge git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/board.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/board.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9cee1d9b4..f3cd81ad9 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; static void omap3_setup_aux_cr(void); +#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); +#endif static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - static void omap3_setup_aux_cr(void) { /* Workaround for Cortex-A8 errata: #454179 #430973 @@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void) } #ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { |