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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-01-06 09:32:42 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-01-06 09:32:42 +0100 |
| commit | 4b0561d84198f8d696fd51cfc27aeac8c7482a8c (patch) | |
| tree | b606414d6bfe1332209a282955233a1d87547f40 /arch/arm/cpu/armv7/exynos/clock_init.h | |
| parent | a891601ce51edbafa1a2750c96a618e4fcbca1c2 (diff) | |
| parent | a5e15bbb42512ee5be53967019e9649816790d7e (diff) | |
| download | olio-uboot-2014.01-4b0561d84198f8d696fd51cfc27aeac8c7482a8c.tar.xz olio-uboot-2014.01-4b0561d84198f8d696fd51cfc27aeac8c7482a8c.zip | |
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/clock_init.h')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock_init.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index c28ff3ab1..a875d0b48 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -10,7 +10,11 @@ #define __EXYNOS_CLOCK_INIT_H enum { +#ifdef CONFIG_EXYNOS5420 + MEM_TIMINGS_MSR_COUNT = 5, +#else MEM_TIMINGS_MSR_COUNT = 4, +#endif }; /* These are the ratio's for configuring ARM clock */ @@ -59,6 +63,18 @@ struct mem_timings { unsigned bpll_mdiv; unsigned bpll_pdiv; unsigned bpll_sdiv; + unsigned kpll_mdiv; + unsigned kpll_pdiv; + unsigned kpll_sdiv; + unsigned dpll_mdiv; + unsigned dpll_pdiv; + unsigned dpll_sdiv; + unsigned ipll_mdiv; + unsigned ipll_pdiv; + unsigned ipll_sdiv; + unsigned spll_mdiv; + unsigned spll_pdiv; + unsigned spll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -115,6 +131,7 @@ struct mem_timings { uint8_t send_zq_init; /* 1 to send this command */ unsigned impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ + uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ }; /** |