diff options
| author | Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> | 2012-08-09 18:29:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:19 +0200 |
| commit | 6995a2893718a54cbd255ea3dd9b6d7306e30cf2 (patch) | |
| tree | cd4a9e07c0a76c4d6f719e07c2c7dffe3ae83f65 /arch/arm/cpu/armv7/am33xx/ddr.c | |
| parent | 25f8bf6eff9e66df850301c5e9e5259807e286f0 (diff) | |
| download | olio-uboot-2014.01-6995a2893718a54cbd255ea3dd9b6d7306e30cf2.tar.xz olio-uboot-2014.01-6995a2893718a54cbd255ea3dd9b6d7306e30cf2.zip | |
am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/ddr.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index cffd4abcf..fd9fc4a72 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,6 +17,7 @@ http://www.ti.com/ #include <asm/arch/cpu.h> #include <asm/arch/ddr_defs.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <asm/emif.h> @@ -46,8 +47,10 @@ void config_sdram(const struct emif_regs *regs) { writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - if (regs->zq_config) + if (regs->zq_config){ writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + } writel(regs->sdram_config, &emif_reg->emif_sdram_config); } |