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| author | Timur Tabi <timur@freescale.com> | 2007-04-30 13:59:50 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-05-01 12:10:26 -0500 |
| commit | f64702b7fc8f8df39d31add770df6e372f9e9ce3 (patch) | |
| tree | d5a47b8ce01f17475dd7cde4cd32abc19774aeca | |
| parent | 54b2d434ae9d01787936f34fe1759cf3d7624ae3 (diff) | |
| download | olio-uboot-2014.01-f64702b7fc8f8df39d31add770df6e372f9e9ce3.tar.xz olio-uboot-2014.01-f64702b7fc8f8df39d31add770df6e372f9e9ce3.zip | |
Fix memory initialization on MPC8349E-mITX
Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.
Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Michael Benedict <MBenedict@twacs.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | board/mpc8349itx/mpc8349itx.c | 3 | ||||
| -rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 5 | ||||
| -rw-r--r-- | include/configs/MPC8349ITX.h | 3 |
3 files changed, 4 insertions, 7 deletions
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 2b3ded176..178b1d36f 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -80,8 +80,7 @@ int fixed_sdram(void) im->ddr.sdram_interval = (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = - DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; udelay(200); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 41a1f1fc7..647813f68 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -693,11 +693,6 @@ long int spd_sdram() #ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; -#else - /* SS_EN = 0, source synchronous disable - * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd - */ - ddr->sdram_clk_cntl = 0x00000000; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 37bbfb336..906339e9d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -154,6 +154,9 @@ #define CFG_MEMTEST_START 0x1000 /* memtest region */ #define CFG_MEMTEST_END 0x2000 +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ #endif |