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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-02-12 01:33:41 +0000 | 
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:10 -0400 | 
| commit | eed7c0f727cf8255b193dfefd21d66dfd6dbae94 (patch) | |
| tree | 7f3e0cb7742beaf5a49d7e3c6e7ff81d6aa895c0 | |
| parent | ef1697e99f482b0e6a64df465ffff77251719abb (diff) | |
| download | olio-uboot-2014.01-eed7c0f727cf8255b193dfefd21d66dfd6dbae94.tar.xz olio-uboot-2014.01-eed7c0f727cf8255b193dfefd21d66dfd6dbae94.zip | |
ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv7.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/omap_common.h | 2 | 
4 files changed, 21 insertions, 11 deletions
| diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e447e..8e66a968a 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -204,17 +204,22 @@ void init_omap_revision(void)  	 */  	unsigned int rev = cortex_rev(); -	switch (rev) { -	case MIDR_CORTEX_A15_R0P0: -		switch (readl(CONTROL_ID_CODE)) { -		case OMAP5430_CONTROL_ID_CODE_ES1_0: -			*omap_si_rev = OMAP5430_ES1_0; -			break; -		case OMAP5432_CONTROL_ID_CODE_ES1_0: -		default: -			*omap_si_rev = OMAP5432_ES1_0; -			break; -		} +	switch (readl(CONTROL_ID_CODE)) { +	case OMAP5430_CONTROL_ID_CODE_ES1_0: +		*omap_si_rev = OMAP5430_ES1_0; +		if (rev == MIDR_CORTEX_A15_R2P2) +			*omap_si_rev = OMAP5430_ES2_0; +		break; +	case OMAP5432_CONTROL_ID_CODE_ES1_0: +		*omap_si_rev = OMAP5432_ES1_0; +		if (rev == MIDR_CORTEX_A15_R2P2) +			*omap_si_rev = OMAP5432_ES2_0; +		break; +	case OMAP5430_CONTROL_ID_CODE_ES2_0: +		*omap_si_rev = OMAP5430_ES2_0; +		break; +	case OMAP5432_CONTROL_ID_CODE_ES2_0: +		*omap_si_rev = OMAP5432_ES2_0;  		break;  	default:  		*omap_si_rev = OMAP5430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 873ccd7df..71935d857 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -57,7 +57,9 @@  /* To be verified */  #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F  #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F  /* STD_FUSE_PROD_ID_1 */  #define STD_FUSE_PROD_ID_1		(CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index ad9a875de..a73630bc4 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -33,6 +33,7 @@  /* Cortex-A15 revisions */  #define MIDR_CORTEX_A15_R0P0	0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2	0x412FC0F2  /* CCSIDR */  #define CCSIDR_LINE_SIZE_OFFSET		0 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2115687ad..459916785 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -542,4 +542,6 @@ static inline u32 omap_revision(void)  #define OMAP5430_SILICON_ID_INVALID	0  #define OMAP5430_ES1_0	0x54300100  #define OMAP5432_ES1_0	0x54320100 +#define OMAP5430_ES2_0  0x54300200 +#define OMAP5432_ES2_0  0x54320200  #endif /* _OMAP_COMMON_H_ */ |