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| author | Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com> | 2013-09-20 18:39:47 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-11-06 09:15:12 +0100 |
| commit | ec4b73f09c384007b274b38052149025e080b138 (patch) | |
| tree | 873b53a50014c59368f2c438917bec1a317212c4 | |
| parent | e5a9a4076f1fb9fb9ce53c2aec32422073bbc66a (diff) | |
| download | olio-uboot-2014.01-ec4b73f09c384007b274b38052149025e080b138.tar.xz olio-uboot-2014.01-ec4b73f09c384007b274b38052149025e080b138.zip | |
fpga: zynqpl: Add dcache flush support
Buffers must be cache and dma aligned.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | drivers/fpga/zynqpl.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c0394c..f2f49b56a 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -177,8 +177,8 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +284,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); |