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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-06-13 12:59:36 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-24 09:51:07 -0400 |
| commit | db2c86d7d71d1be0ac0fe702493faf9302639235 (patch) | |
| tree | 31a0c3a4a35fa7af0ff139b5b036ae22ef76986f | |
| parent | ee8b1e29597bcf18bfebd6fd8eccc8e245046352 (diff) | |
| download | olio-uboot-2014.01-db2c86d7d71d1be0ac0fe702493faf9302639235.tar.xz olio-uboot-2014.01-db2c86d7d71d1be0ac0fe702493faf9302639235.zip | |
MIPS: mips32/cache.S: use v1 register for indirect function calls
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| -rw-r--r-- | arch/mips/cpu/mips32/cache.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index d3f156e48..12f656cad 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra) */ move a1, t2 move a2, t8 - PTR_LA t7, mips_init_icache - jalr t7 + PTR_LA v1, mips_init_icache + jalr v1 /* * then initialize D-cache. */ move a1, t3 move a2, t8 - PTR_LA t7, mips_init_dcache - jalr t7 + PTR_LA v1, mips_init_dcache + jalr v1 jr RA END(mips_cache_reset) |