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| author | Stefan Roese <sr@denx.de> | 2009-09-24 14:10:30 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-09-28 10:46:05 +0200 |
| commit | b306db2f1bf561b5823a655c677fe28cfad80cfb (patch) | |
| tree | 8a20bc22a8defaaed048009372119f13fb93ccfa | |
| parent | 95b602bab5fec2fffab07a01ea3947c70d1bacc1 (diff) | |
| download | olio-uboot-2014.01-b306db2f1bf561b5823a655c677fe28cfad80cfb.tar.xz olio-uboot-2014.01-b306db2f1bf561b5823a655c677fe28cfad80cfb.zip | |
ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead
Additionally some whitespace coding style fixes.
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | board/g2000/g2000.c | 15 | ||||
| -rw-r--r-- | cpu/ppc4xx/40x_spd_sdram.c | 27 |
2 files changed, 20 insertions, 22 deletions
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 092a3d8a1..03cd6b884 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -114,18 +114,17 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL ); - mtsdram0( SDRAM0_RTR , MEM_RTR_INIT_VAL ); - mtsdram0( SDRAM0_PMIT , MEM_PMIT_INIT_VAL ); - mtsdram0( SDRAM0_B0CR , MEM_MB0CF_INIT_VAL ); - mtsdram0( SDRAM0_B1CR , MEM_MB1CF_INIT_VAL ); - mtsdram0( SDRAM0_TR , MEM_SDTR1_INIT_VAL ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL); + mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL); + mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL); + mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL); + mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL); + mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); - mtsdram0( SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); + mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE); return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index c50f67308..5e6dbe333 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -422,32 +422,31 @@ long int spd_sdram(int(read_spd)(uint addr)) * program all the registers. * -------------------------------------------------------------------*/ -#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ - mtsdram0( SDRAM0_CFG, 0 ); + mtsdram(SDRAM0_CFG, 0); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( SDRAM0_BESR0 , sdram0_besr0 ); - mtsdram0( SDRAM0_BESR1 , sdram0_besr1 ); - mtsdram0( SDRAM0_ECCCFG , sdram0_ecccfg ); - mtsdram0( SDRAM0_ECCESR, sdram0_eccesr ); + mtsdram(SDRAM0_BESR0, sdram0_besr0); + mtsdram(SDRAM0_BESR1, sdram0_besr1); + mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); + mtsdram(SDRAM0_ECCESR, sdram0_eccesr); #endif - mtsdram0( SDRAM0_RTR , sdram0_rtr ); - mtsdram0( SDRAM0_PMIT , sdram0_pmit ); - mtsdram0( SDRAM0_B0CR , sdram0_b0cr ); - mtsdram0( SDRAM0_B1CR , sdram0_b1cr ); + mtsdram(SDRAM0_RTR, sdram0_rtr); + mtsdram(SDRAM0_PMIT, sdram0_pmit); + mtsdram(SDRAM0_B0CR, sdram0_b0cr); + mtsdram(SDRAM0_B1CR, sdram0_b1cr); #ifndef CONFIG_405EP /* not on PPC405EP */ - mtsdram0( SDRAM0_B2CR , sdram0_b2cr ); - mtsdram0( SDRAM0_B3CR , sdram0_b3cr ); + mtsdram(SDRAM0_B2CR, sdram0_b2cr); + mtsdram(SDRAM0_B3CR, sdram0_b3cr); #endif - mtsdram0( SDRAM0_TR , sdram0_tr ); + mtsdram(SDRAM0_TR, sdram0_tr); /* SDRAM have a power on delay, 500 micro should do */ udelay(500); sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; if (ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK; - mtsdram0(SDRAM0_CFG, sdram0_cfg); + mtsdram(SDRAM0_CFG, sdram0_cfg); return (total_size); } |